?? arm10.v
字號:
end 8'h63: begin // Undefined Instruction if (ir[4] == 1'b1) undefined; else // Load Word, register, write back, post dec ldrw; end 8'h64: begin // Undefined Instruction if (ir[4] == 1'b1) undefined; else // Store Byte, register, no write back, post dec strw; end 8'h65: begin // Undefined Instruction if (ir[4] == 1'b1) undefined; else // Load Byte, register, no write back, post dec ldrw; end 8'h66: begin // Undefined Instruction if (ir[4] == 1'b1) undefined; else // Store Byte, register, write back, post dec strw; end 8'h67: begin // Undefined Instruction if (ir[4] == 1'b1) undefined; else // Load Byte, register, write back, post dec ldrw; end 8'h68: begin // Undefined Instruction if (ir[4] == 1'b1) undefined; else // Store Word, register, no write back, post inc strw; end 8'h69: begin // Undefined Instruction if (ir[4] == 1'b1) undefined; else // Load Word, register, no write back, post inc ldrw; end 8'h6A: begin // Undefined Instruction if (ir[4] == 1'b1) undefined; else // Store Word, register, write back, post inc strw; end 8'h6B: begin // Undefined Instruction if (ir[4] == 1'b1) undefined; else // Load Word, register, write back, post inc ldrw; end 8'h6C: begin // Undefined Instruction if (ir[4] == 1'b1) undefined; else // Store Byte, register, no write back, post inc strw; end 8'h6D: begin // Undefined Instruction if (ir[4] == 1'b1) undefined; else // Load Byte, register, no write back, post inc ldrw; end 8'h6E: begin // Undefined Instruction if (ir[4] == 1'b1) undefined; else // Store Byte, register, write back, post inc strw; end 8'h6F: begin // Undefined Instruction if (ir[4] == 1'b1) undefined; else // Load Byte, register, write back, post inc ldrw; end 8'h70: begin // Undefined Instruction if (ir[4] == 1'b1) undefined; else // Store Word, register, no write back, pre dec strw; end 8'h71: begin // Undefined Instruction if (ir[4] == 1'b1) undefined; else // Load Word, register, no write back, pre dec ldrw; end 8'h72: begin // Undefined Instruction if (ir[4] == 1'b1) undefined; else // Store Word, register, write back, pre dec strw; end 8'h73: begin // Undefined Instruction if (ir[4] == 1'b1) undefined; else // Load Word, register, write back, pre dec ldrw; end 8'h74: begin // Undefined Instruction if (ir[4] == 1'b1) undefined; else // Store Byte, register, no write back, pre dec strw; end 8'h75: begin // Undefined Instruction if (ir[4] == 1'b1) undefined; else // Load Byte, register, no write back, pre dec ldrw; end 8'h76: begin // Undefined Instruction if (ir[4] == 1'b1) undefined; else // Store Byte, register, write back, pre dec strw; end 8'h77: begin // Undefined Instruction if (ir[4] == 1'b1) undefined; else // Load Byte, register, write back, pre dec ldrw; end 8'h78: begin // Undefined Instruction if (ir[4] == 1'b1) undefined; else // Store Word, register, no write back, pre inc strw; end 8'h79: begin // Undefined Instruction if (ir[4] == 1'b1) undefined; else // Load Word, register, no write back, pre inc ldrw; end 8'h7A: begin // Undefined Instruction if (ir[4] == 1'b1) undefined; else // Store Word, register, write back, pre inc strw; end 8'h7B: begin // Undefined Instruction if (ir[4] == 1'b1) undefined; else // Load Word, register, write back, pre inc ldrw; end 8'h7C: begin // Undefined Instruction if (ir[4] == 1'b1) undefined; else // Store Byte, register, no write back, pre inc strw; end 8'h7D: begin // Undefined Instruction if (ir[4] == 1'b1) undefined; else // Load Byte, register, no write back, pre inc ldrw; end 8'h7E: begin // Undefined Instruction if (ir[4] == 1'b1) undefined; else // Store Byte, register, write back, pre inc strw; end 8'h7F: begin // Undefined Instruction if (ir[4] == 1'b1) undefined; else // Load Byte, register, write back, pre inc ldrw; end // Store Multiple, no write back, post dec 8'h80: stm; // Load Multiple, no write back, post dec 8'h81: ldm; // Store Multiple, write back, post dec 8'h82: stm; // Load Multiple, write back, post dec 8'h83: ldm; // Store Multiple, flags, no write back, post dec 8'h84: stm; // Load Multiple, flags, no write back, post dec 8'h85: ldm; // Store Multiple, flags, write back, post dec 8'h86: stm; // Load Multiple, flags, write back, post dec 8'h87: ldm; // Store Multiple, no write back, post inc 8'h88: stm; 8'h89: ldm; // Store Multiple, write back, post inc 8'h8A: stm; // Load Multiple, write back, post inc 8'h8B: ldm; // Store Multiple, flags, no write back, post inc 8'h8C: stm; // Load Multiple, flags, no write back, post inc 8'h8D: ldm; // Store Multiple, flags, write back, post inc 8'h8E: stm; // Load Multiple, flags, write back, post inc 8'h8F: ldm; // Store Multiple, no write back, pre dec 8'h90: stm; // Load Multiple, no write back, pre dec 8'h91: ldm; // Store Multiple, write back, pre dec 8'h92: stm; // Load Multiple, write back, pre dec 8'h93: ldm; // Store Multiple, flags, no write back, pre dec 8'h94: stm; // Load Multiple, flags, no write back, pre dec 8'h95: ldm; // Store Multiple, flags, write back, pre dec 8'h96: stm; // Load Multiple, flags, write back, pre dec 8'h97: ldm; // Store Multiple, no write back, pre inc 8'h98: stm; // Load Multiple, no write back, pre inc 8'h99: ldm; // Store Multiple, write back, pre inc 8'h9A: stm; // Load Multiple, write back, pre inc 8'h9B: ldm; // Store Multiple, flags, no write back, pre inc 8'h9C: stm; // Load Multiple, flags, no write back, pre inc 8'h9D: ldm; // Store Multiple, flags, write back, pre inc 8'h9E: stm; // Load Multiple, flags, write back, pre inc 8'h9F: ldm; // Branch Forward 8'hA0, 8'hA1, 8'hA2, 8'hA3, 8'hA4, 8'hA5, 8'hA6, 8'hA7: br; // Branch Backward 8'hA8, 8'hA9, 8'hAA, 8'hAB, 8'hAC, 8'hAD, 8'hAE, 8'hAF: br; // Branch and Link Forward 8'hB0, 8'hB1, 8'hB2, 8'hB3, 8'hB4, 8'hB5, 8'hB6, 8'hB7: br; // Branch and Link Backward 8'hB8, 8'hB9, 8'hBA, 8'hBB, 8'hBC, 8'hBD, 8'hBE, 8'hBF: br; // Coprocessor Operations 8'hC0, 8'hC1, 8'hC2, 8'hC3, 8'hC4, 8'hC5, 8'hC6, 8'hC7, 8'hC8, 8'hC9, 8'hCA, 8'hCB, 8'hCC, 8'hCD, 8'hCE, 8'hCF, 8'hD0, 8'hD1, 8'hD2, 8'hD3, 8'hD4, 8'hD5, 8'hD6, 8'hD7, 8'hD8, 8'hD9, 8'hDA, 8'hDB, 8'hDC, 8'hDD, 8'hDE, 8'hDF, 8'hE0, 8'hE1, 8'hE2, 8'hE3, 8'hE4, 8'hE5, 8'hE6, 8'hE7, 8'hE8, 8'hE9, 8'hEA, 8'hEB, 8'hEC, 8'hED, 8'hEE, 8'hEF: cop; // Software Interrupt 8'hF0, 8'hF1, 8'hF2, 8'hF3, 8'hF4, 8'hF5, 8'hF6, 8'hF7, 8'hF8, 8'hF9, 8'hFA, 8'hFB, 8'hFC, 8'hFD, 8'hFE, 8'hFF: swi; endcase end end/*------------------------------------------------------------------------ Functions & Tasks------------------------------------------------------------------------*/ //MUL, MLA, MULS, & MLAS Instructions task mul; reg [31:0] temp; //used to get bits of a reg reg [31:0] tmp_psr; //copy of CPSR reg [63:0] m_res; //64-bit result begin tmp_psr = CPSR; if (ir[21] == 1'b1) m_res = reg_decode(map(Rm))*reg_decode(map(Rs))+reg_decode(map(Rd)); else m_res = reg_decode(map(Rm))*reg_decode(map(Rs)); //Setup for Writing Result inst_result[0] = m_res[31:0]; result_dest[0] = map(Rn); result_valid[0] = 1'b1; if (S == 1'b1) begin if (m_res[31:0] == 32'h00000000) begin psr_result[0] = {3'b01, tmp_psr[29:0]}; psr_dest[0] = 3'h0; psr_valid[0]= 1'b1; end else begin psr_result[0] = {m_res[31], 1'b0, tmp_psr[29:0]};?? 快捷鍵說明
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