/*****************************************************************************$RCSfile: testarm.s,v $$Revision: 1.11 $$Author: kohlere $$Date: 1999/05/06 20:09:07 $$State: Exp $$Source: /home/lefurgy/tmp/ISC-repository/isc/hardware/ARM10/behavioral/testarm.s,v $*****************************************************************************/		begin:@set up a few register valuesAND 	R0, R0, #0	@R0 = 0AND 	R1, R1, #0	@R1 = 0AND 	R2, R2, #0	@R2 = 0AND 	R3, R3, #0	@R3 = 0ORR	R0, R0, #1	@R0 = 1ORR 	R1, R0, #2	@R1 = 3ADD	R2, R0, R1	@R2 = 4@test a simple loop, ends with R2=0, R1=-37 (0xFFFFFFDB)loop: SUB	R1, R1, #10	@R1 = R1 - 10 => -37SUBS	R2, R2, #1	@R2 = R2 - 1  => 0BNE 	loop@call some subroutinesBL	alu		@tests the alu functions (R0-R13 = 0)BL	stw		@tests simple store/load of wordsmov	sp, #1000	@Set up a Stack Pointer BL	testldmstm	@test ldm/stm functions of wordsBL	testswp		@test swp functionsBL	testmull	@test Signed/Unsigned MultiplicationBL	testmsr		@test MSR/MRS InstructionsBL	teststrh	@test Halfword/Byte Loads/Storesmov 	sp, #1000	@Reset the stack PointerBL	main		@Doesn't Work (wasn't linked)teststrh:mov 	R0, #0xff	@R0 = 0x000000ffmov 	R1, #0xaa00	@R1 = 0x0000aa00ORR 	R0,R0,R1	@R0 = 0x0000aaffmov 	R1, #0x550000	@R1 = 0x00550000ORR 	R0,R0,R1        @R0 = 0x0055aaffmov 	R1, #0x10000    @R1 = 0x00010000strh 	R0, [R1],#2     @[10000] = 0xXXXXaaffldr 	R6, [R1,#-2]    @R6 = 0xXXXXaaffstrh 	R0, [R1],#2     @[10000] = 0xaaffaaffldr 	R7, [R1,#-4]    @R7 = 0xaaffaaffldrh 	R2, [R1,#-2]    @R2 = 0x0000aaffldrsh 	R3, [R1,#-2]    @R3 = 0xffffaaffldrsb 	R4, [R1,#-2]    @R4 = 0xffffffffldrsb 	R5, [R1,#-1]    @R5 = 0xffffffaasub 	R1,R1,#4        @R1 = 0x10000str 	R0,[R1]         @[10000] = 0055aaffadd 	R1,R1,#1        @R1 = 0x10001ldr 	R9,[R1]         @R9 = 0xff0055aaadd 	R1,R1,#1        @R1 = 0x10002ldr 	R9,[R1]         @R9 = 0xaaff0055add 	R1,R1,#1        @R1 = 0x10003ldr	R9,[R1]         @R9 = 0x55aaff00sub 	R1,R1,#2        @R1 = 0x10001str 	R0,[R1]         @[10000] = 0x0055aaffldr 	R9,[R1]		@R9 = 0xff0055aasub 	R1,R1,#1        @R9 = 0x10000ldr 	R9,[R1]		@R9 = 0x0055aaffmov 	PC, R14		@Returnalu:	MOVS	R0, #-1		@R0 = -1 (0xFFFFFFFF)ADDS	R0, R0, #1	@R0 = 0SUBS	R0, R0, #1	@R0 = -1MOVS 	R2, #255	@R2 = 0x000000FFEORS	R1, R0, R2	@R1 = 0xFFFFFFFF00RSBS	R0, R0, #1	@R0 = 2ADCS	R0, R0, R0	@R0 = 4SBCS	R0, R0, R0	@R0 = -1RSCS	R2, R0, R2	@R2 = 0x000000FF)SUBS	R2, R2, #1	@R2 = 0x000000FE)ORRS	R1, R1, R2	@R1 = 0xFFFFFFFEMOVS	R0, #1		@R0 = 1BICS	R3, R0, R2	@R3 = 1ORRS   R1,R0,R1,LSR #28 @R1 = 0x0000000FADDS	R1, R1, #1	@R1 = 0x00000010ADDS	R0, R0, #65536 	@R0 = 0x00010001SUBS 	R0,R0,R3,LSL R1 @R0 = 0x00000001 (R0 = R0 - (R3 << 15))ANDS   R0,R0,R3,ROR #31 @R0 = 0x00000000 ADDS	R3,R3,R1,ASR #1 @R3 = 0x00000009ANDS	R2, R2, #0	@R2 = 0x00000000ANDS 	R1, R1, #0	@R1 = 0x00000000MOVS	PC, R14		@Returntestmull:mov 	R0, #2147483649	@R0 = 0x80000001mov	R1, #4		@R1 = 0x4UMULL 	R2,R3,R1,R0	@R2 = 0x4, R3 = 0x2SMULL 	R4,R5,R1,R0	@R4 = 0x4, R5 = 0xFFFFFFFEMOV 	PC, R14		@Returnstw:mov R0, #0		@R0 = 0x0mov R1, #10		@R1 = 0xAmov R2, #100		@R2 = 0x64mov R3, #1000		@R3 = 0x3E8mov R4, #32768		@R4 = 0x8000strt R1, [R4], #8	@R1 -> [R4], R4 += 8strt R2, [R4], #8	@R2 -> [R4], R4 += 8strt R3, [R4], #8	@R3 -> [R4], R4 += 8mov R1, #0		@R1 = 0mov R2, #0		@R2 = 0mov R3, #0		@R3 = 0ldr R1, [R4, #-8]!	@R4 -= 8, R1 = 0x3E8ldr R2, [R4, #-8]!	@R4 -= 8, @2 = 0x64ldr R3, [R4, #-8]!	@R4 -= 8, R3 = 0xAMOV     PC, R14         @Returntestldmstm:mov R0, #0		@R0=0	mov R1, #1		@R1=1mov R2, #2		@R2=2mov R3, #3		@R3=3mov R4, #65536		@R4=0x10000mov R5, #196608		@R5=0x30000mov R6, #458752		@R6=0x70000mov R7, #983040		@R7=0xF0000mov R8, #32768		@R8=0x8000mov R9, #16384		@R9=0x4000stmia r8!, {r0-r7}	@Store R0-R7, R8=8020ldmia r9, {r0-r7}       @clear R0-R7ldmdb r8!, {r0-r7}	@Load R0-R7, R8=8000stmib r8!, {r0-r7}	@Store R0-R7, R8=8020ldmia r9, {r0-r7}       @clear R0-R7ldmda r8!, {r0-r7}	@Load R0-R7, R8=8000stmda r8!, {r0-r7}	@Store R0-R7, R8=7FE0ldmia r9, {r0-r7}       @clear R0-R7ldmib r8!, {r0-r7}	@Load R0-R7, R8=8000stmdb r8!, {r0-r7}	@Store R0-R7, R8=7FE0ldmia r9, {r0-r7}       @clear R0-R7	ldmia r8!, {r0-r7}	@Load R0-R7, R8=8000ldmia r9, {r0-r7}       @clear R0-R7MOV     PC, R14         @Returntestswp:		@([8000] = 0x000000FF)mov R0, #0		@R0=0x0mov R1, #1		@R1=0x1mov R2, #2		@R2=0x2mov R3, #49152		@R3=0xC000swp R0, R1, [R3]        @R0 = 0xFF, [C000] = 0x1swp R2, R2, [R3]        @R2 = 0x1, [C000] = 0x2swp R2, R3, [R3]        @R2 = 0x2, [C000] = 0xC000swp R0, R0, [R3]        @R0 = 0xC000, [C000] = 0xFFswpb R0, R0, [R3]       @R0 = 0x000000FF, [C000] = 0x0swp R0, R0, [R3]        @R0 = 0x0, [C000] = 0x000000FFMOV     PC, R14         @Return@Tests for MSR/MRS Instructionstestmsr:mov R0, #16     @Set R0 to USR Modemov R1, #17     @Set R1 to FIQ Modemov R2, #18     @Set R2 to IRQ Modemov R3, #19     @Set R3 to SVC Modemov R4, #23     @Set R4 to ABT Modemov R5, #27     @Set R5 to UND modemov R6, #31     @Set R6 to SYS Modemov R7, #4026531840     @R7 = 0xF00000000mov R8, #2147483648     @R8 = 0x800000000MSR cpsr_all, R1                @CPSR = 0x00000011 (FIQ Mode)MSR spsr_all, R7                @SPSR_FIQ = 0xF0000000MRS R8, spsr                    @R16 = 0xF00000000MRS R9, spsr                    @R17 = 0xF00000000MRS R10, spsr                   @R18 = 0xF00000000MRS R11, spsr                   @R19 = 0xF00000000MRS R12, spsr                   @R20 = 0xF00000000MRS R13, spsr                   @R21 = 0xF00000000MRS R14, spsr                   @R22 = 0xF00000000MSR cpsr_all, R2                @CPSR = 0x00000012 (IRQ Mode)MSR spsr_all, R8                @SPSR_IRQ = 0x80000000MRS R13, spsr                   @R27 = 0x800000000MRS R14, spsr                   @R28 = 0x800000000MSR cpsr_all, R3                @CPSR = 0x00000013 (SVC Mode)MSR spsr_all, R7                @SPSR_SVC = 0xF0000000MRS R10, spsr                   @R10 = 0xF00000000mov R3, R14                     @Copy Link Register to R3MSR cpsr_all, R4                @CPSR = 0x00000017 (ABT Mode)MSR spsr_all, R8                @SPSR_ABT = 0x80000000MRS R13, spsr                   @R25 = 0x80000000MRS R14, spsr                   @R26 = 0x80000000MSR cpsr_all, R5                @CPSR = 0x0000001B (UND Mode)MSR spsr_all, R7                @SPSR_UND = 0xF0000000MRS R13, spsr                   @R29 = 0xF00000000MRS R14, spsr                   @R30 = 0xF00000000MSR cpsr_all, R6                @CPSR = 0x0000001F (SYS Mode)MRS R13, cpsr                   @R13 = 0x0000001Fmov R14, R3                     @Copy Link Register to R14MSR cpsr_all, R0                @CPSR = 0x00000010 (User Mode)MSR cpsr_all, R7                @CPSR = 0xF0000010MSR cpsr_flg, R8                @CPSR = 0x80000010MSR cpsr_flg, #2684354560       @CPSR = 0xA0000010MRS R9, cpsr                    @R9 = 0xA0000010mov PC, R14			@Return.text.align 0.global mainmain:        @ args = 0, pretend = 0, frame = 24        @ frame_needed = 1, current_function_anonymous_args = 0        mov     ip, sp        stmfd   sp!, {r4, fp, ip, lr, pc}        sub     fp, ip, #4        sub     sp, sp, #24        bl      __gccmain        mov     r3, #0        str     r3, [fp, #-40]        mov     r3, #0        str     r3, [fp, #-40].L2:        ldr     r3, [fp, #-40]        cmp     r3, #5        ble     .L5        b       .L3.L5:        ldr     r3, [fp, #-40]        cmp     r3, #1        bgt     .L6        ldr     r3, [fp, #-40]        mov     r2, r3        mov     r3, r2, asl #2        sub     r2, fp, #36        mov     r1, #1        str     r1, [r2, r3]        b       .L4.L6:        ldr     r3, [fp, #-40]        mov     r2, r3        mov     r3, r2, asl #2        sub     r2, fp, #36        ldr     ip, [fp, #-40]        sub     r1, ip, #1        mov     ip, r1        mov     r1, ip, asl #2        sub     ip, fp, #36        ldr     r4, [fp, #-40]        sub     lr, r4, #2        mov     r4, lr        mov     lr, r4, asl #2        sub     r4, fp, #36        ldr     r1, [ip, r1]        ldr     ip, [r4, lr]        add     r1, r1, ip        str     r1, [r2, r3].L7:.L4:        ldr     r3, [fp, #-40]        add     r2, r3, #1        str     r2, [fp, #-40]        b       .L2.L3:        mov     r0, #0        b       .L1.L1:        ldmea   fp, {r4, fp, sp, pc}