ior => rx8:u_rx8.ior
ior => write_reg:u_read_write.ior
ior => ad~8.IN0
ior => ad~17.IN0
ior => ad~26.IN0
ior => ad~37.IN0
ior => ad~46.IN0
ior => ad~55.IN0
ior => ad~64.IN0
ior => ad~73.IN0
ior => ad~82.IN0
ior => ad~91.IN0
ior => ad~100.IN0
ior => ad~109.IN0
ior => ad~118.IN0
ior => ad~127.IN0
ior => ad~136.IN0
ior => ad~145.IN0
ior => ad~154.IN0
iow => tx8:u_tx8.iow
iow => generate_int:u_int.iow
iow => time_out:u_time_out.iow
iow => do_adc:u_ad.iow
iow => write_reg:u_read_write.iow
o_cda[0] <= do_adc:u_ad.cda[0]
o_cda[1] <= do_adc:u_ad.cda[1]
o_cda[2] <= do_adc:u_ad.cda[2]
rd_ad_l <= do_adc:u_ad.rd_adl
rd_ad_h <= do_adc:u_ad.rd_adh
o_start_ad <= do_adc:u_ad.start_ad
eoc_state => do_adc:u_ad.eoc_state
ale => write_reg:u_read_write.ale
sel => ~NO_FANOUT~
SEL_eeprom_eprom <= <VCC>
urgency_put_opt_in => generate_int:u_int.urgency_put_opt_in
ready_reset_opt_in => generate_int:u_int.ready_reset_opt_in
urgency_put_opt_inx <= generate_int:u_int.urgency_put_opt_inx
ready_reset_opt_inx <= generate_int:u_int.ready_reset_opt_inx
conn_on0 <= write_reg:u_read_write.conn_on
conn_on1 <= write_reg:u_read_write.conn_on
conn_on2 <= write_reg:u_read_write.conn_on
conn_on3 <= write_reg:u_read_write.conn_on
torpedo_on_drv <= torpedo_on_drv~0.DB_MAX_OUTPUT_PORT_TYPE
pesudo_LED_drv <= write_reg:u_read_write.pesudo_LED
run_led_drv <= write_reg:u_read_write.run_led
rio_led_drv <= write_reg:u_read_write.rio_led
ad_led_drv <= write_reg:u_read_write.ad_led
cpu_led_drv <= write_reg:u_read_write.cpu_led
tube_drv <= write_reg:u_read_write.tube
AborneN28v_drv <= write_reg:u_read_write.naborne
AborneP28v_drv <= write_reg:u_read_write.paborne
gulock_drv <= gulock_drv~0.DB_MAX_OUTPUT_PORT_TYPE
cmdr_drv <= cmdr_drv~0.DB_MAX_OUTPUT_PORT_TYPE
sddr_drv <= sddr_drv~0.DB_MAX_OUTPUT_PORT_TYPE
rd_pesudo_key <= <GND>
psen <= psenx.DB_MAX_OUTPUT_PORT_TYPE
psenx => psen.DATAIN
txd <= tx8:u_tx8.tx
rxd => rx8:u_rx8.rx
p10 <= p10~1.DB_MAX_OUTPUT_PORT_TYPE
p11 <= p11~0.DB_MAX_OUTPUT_PORT_TYPE
p12 <= p12~0.DB_MAX_OUTPUT_PORT_TYPE
p13 <= p13~0.DB_MAX_OUTPUT_PORT_TYPE
p14 <= p14~0.DB_MAX_OUTPUT_PORT_TYPE
p15 <= p15~0.DB_MAX_OUTPUT_PORT_TYPE
p16 <= p16~0.DB_MAX_OUTPUT_PORT_TYPE
p17 <= p17~0.DB_MAX_OUTPUT_PORT_TYPE
EEPROM_IOW <= <GND>
EEPROM_IOR <= <GND>


|cpu|gen_1mhz:u_p1mhz
p12mhz => P1MHz_clk_cnt[2].CLK
p12mhz => P1MHz_clk_cnt[1].CLK
p12mhz => P1MHz_clk_cnt[0].CLK
p12mhz => P1MHz_clk.CLK
p12mhz => P1MHz_clk_cnt[3].CLK
rst => ~NO_FANOUT~
P1MHz <= P1MHz_clk.DB_MAX_OUTPUT_PORT_TYPE
p1khz <= t_p1khz.DB_MAX_OUTPUT_PORT_TYPE


|cpu|write_reg:u_read_write
ale => wri_reg8:u_adr.iow
ad_in[0] => wri_reg8:u_a3_reg.data_in[0]
ad_in[0] => wri_reg8:u_y7b_reg.data_in[0]
ad_in[0] => wri_reg8:u_reg_led.data_in[0]
ad_in[0] => wri_reg8:u_adr.data_in[0]
ad_in[0] => t_err_cm_code[0].DATAIN
ad_in[0] => t_err_sd_code[0].DATAIN
ad_in[0] => flash_mode_led~reg0.DATAIN
ad_in[0] => flash_ready_led~reg0.DATAIN
ad_in[0] => XT~reg0.DATAIN
ad_in[1] => wri_reg8:u_a3_reg.data_in[1]
ad_in[1] => wri_reg8:u_y7b_reg.data_in[1]
ad_in[1] => wri_reg8:u_reg_led.data_in[1]
ad_in[1] => wri_reg8:u_adr.data_in[1]
ad_in[1] => t_err_cm_code[1].DATAIN
ad_in[1] => t_err_sd_code[1].DATAIN
ad_in[2] => wri_reg8:u_a3_reg.data_in[2]
ad_in[2] => wri_reg8:u_y7b_reg.data_in[2]
ad_in[2] => wri_reg8:u_reg_led.data_in[2]
ad_in[2] => wri_reg8:u_adr.data_in[2]
ad_in[2] => t_err_cm_code[2].DATAIN
ad_in[2] => t_err_sd_code[2].DATAIN
ad_in[3] => wri_reg8:u_a3_reg.data_in[3]
ad_in[3] => wri_reg8:u_y7b_reg.data_in[3]
ad_in[3] => wri_reg8:u_reg_led.data_in[3]
ad_in[3] => wri_reg8:u_adr.data_in[3]
ad_in[3] => t_err_sd_code[3].DATAIN
ad_in[3] => t_err_cm_code[3].DATAIN
ad_in[4] => wri_reg8:u_a3_reg.data_in[4]
ad_in[4] => wri_reg8:u_y7b_reg.data_in[4]
ad_in[4] => wri_reg8:u_reg_led.data_in[4]
ad_in[4] => wri_reg8:u_adr.data_in[4]
ad_in[4] => t_err_cm_code[4].DATAIN
ad_in[5] => wri_reg8:u_a3_reg.data_in[5]
ad_in[5] => wri_reg8:u_y7b_reg.data_in[5]
ad_in[5] => wri_reg8:u_reg_led.data_in[5]
ad_in[5] => wri_reg8:u_adr.data_in[5]
ad_in[5] => t_err_cm_code[5].DATAIN
ad_in[6] => wri_reg8:u_a3_reg.data_in[6]
ad_in[6] => wri_reg8:u_y7b_reg.data_in[6]
ad_in[6] => wri_reg8:u_reg_led.data_in[6]
ad_in[6] => wri_reg8:u_adr.data_in[6]
ad_in[6] => t_err_cm_code[6].DATAIN
ad_in[7] => wri_reg8:u_a3_reg.data_in[7]
ad_in[7] => wri_reg8:u_y7b_reg.data_in[7]
ad_in[7] => wri_reg8:u_reg_led.data_in[7]
ad_in[7] => wri_reg8:u_adr.data_in[7]
ad_in[7] => t_err_sd_code[7].DATAIN
ad_in[7] => t_err_cm_code[7].DATAIN
sa_h[8] => reduce_nor~0.IN13
sa_h[8] => reduce_nor~1.IN13
sa_h[8] => reduce_nor~2.IN13
sa_h[8] => reduce_nor~3.IN13
sa_h[8] => reduce_nor~4.IN13
sa_h[8] => reduce_nor~5.IN13
sa_h[8] => reduce_nor~6.IN13
sa_h[8] => reduce_nor~7.IN13
sa_h[9] => reduce_nor~0.IN12
sa_h[9] => reduce_nor~1.IN12
sa_h[9] => reduce_nor~2.IN12
sa_h[9] => reduce_nor~3.IN12
sa_h[9] => reduce_nor~4.IN12
sa_h[9] => reduce_nor~5.IN12
sa_h[9] => reduce_nor~6.IN12
sa_h[9] => reduce_nor~7.IN12
sa_h[10] => reduce_nor~0.IN11
sa_h[10] => reduce_nor~1.IN11
sa_h[10] => reduce_nor~2.IN11
sa_h[10] => reduce_nor~3.IN11
sa_h[10] => reduce_nor~4.IN11
sa_h[10] => reduce_nor~5.IN11
sa_h[10] => reduce_nor~6.IN11
sa_h[10] => reduce_nor~7.IN11
sa_h[11] => reduce_nor~0.IN10
sa_h[11] => reduce_nor~1.IN10
sa_h[11] => reduce_nor~2.IN10
sa_h[11] => reduce_nor~3.IN10
sa_h[11] => reduce_nor~4.IN10
sa_h[11] => reduce_nor~5.IN10
sa_h[11] => reduce_nor~6.IN10
sa_h[11] => reduce_nor~7.IN10
sa_h[12] => reduce_nor~0.IN9
sa_h[12] => reduce_nor~1.IN9
sa_h[12] => reduce_nor~2.IN9
sa_h[12] => reduce_nor~3.IN9
sa_h[12] => reduce_nor~4.IN9
sa_h[12] => reduce_nor~5.IN9
sa_h[12] => reduce_nor~6.IN9
sa_h[12] => reduce_nor~7.IN9
sa_h[13] => reduce_nor~0.IN8
sa_h[13] => reduce_nor~1.IN8
sa_h[13] => reduce_nor~2.IN8
sa_h[13] => reduce_nor~3.IN8
sa_h[13] => reduce_nor~4.IN8
sa_h[13] => reduce_nor~5.IN8
sa_h[13] => reduce_nor~6.IN8
sa_h[13] => reduce_nor~7.IN8
sa_h[14] => reduce_nor~0.IN14
sa_h[14] => reduce_nor~1.IN14
sa_h[14] => reduce_nor~2.IN14
sa_h[14] => reduce_nor~3.IN14
sa_h[14] => reduce_nor~4.IN14
sa_h[14] => reduce_nor~5.IN14
sa_h[14] => reduce_nor~6.IN14
sa_h[14] => reduce_nor~7.IN14
sa_h[15] => reduce_nor~0.IN15
sa_h[15] => reduce_nor~1.IN15
sa_h[15] => reduce_nor~2.IN15
sa_h[15] => reduce_nor~3.IN15
sa_h[15] => reduce_nor~4.IN15
sa_h[15] => reduce_nor~5.IN15
sa_h[15] => reduce_nor~6.IN15
sa_h[15] => reduce_nor~7.IN15
iow => t_err_cm_code[6].CLK
iow => t_err_cm_code[5].CLK
iow => t_err_cm_code[4].CLK
iow => t_err_cm_code[3].CLK
iow => t_err_cm_code[2].CLK
iow => t_err_cm_code[1].CLK
iow => t_err_cm_code[0].CLK
iow => t_err_sd_code[7].CLK
iow => t_err_sd_code[3].CLK
iow => t_err_sd_code[2].CLK
iow => t_err_sd_code[1].CLK
iow => t_err_sd_code[0].CLK
iow => flash_mode_led~reg0.CLK
iow => flash_ready_led~reg0.CLK
iow => XT~reg0.CLK
iow => wri_reg8:u_a3_reg.iow
iow => wri_reg8:u_y7b_reg.iow
iow => wri_reg8:u_reg_led.iow
iow => t_err_cm_code[7].CLK
ior => ~NO_FANOUT~
rst => wri_reg8:u_a3_reg.rst
rst => wri_reg8:u_y7b_reg.rst
rst => wri_reg8:u_reg_led.rst
rst => wri_reg8:u_adr.rst
rst => t_err_cm_code[6].ACLR
rst => t_err_cm_code[5].ACLR
rst => t_err_cm_code[4].PRESET
rst => t_err_cm_code[3].PRESET
rst => t_err_cm_code[2].ACLR
rst => t_err_cm_code[1].ACLR
rst => t_err_cm_code[0].ACLR
rst => t_err_sd_code[3].ACLR
rst => t_err_cm_code[7].ACLR
rst => t_err_sd_code[2].PRESET
rst => t_err_sd_code[1].ACLR
rst => t_err_sd_code[0].ACLR
rst => t_err_sd_code[7].ACLR
rst => process2~0.IN0
rst => flash_ready_led~reg0.ACLR
rst => XT~reg0.ACLR
sa_l[0] <= wri_reg8:u_adr.data_out[0]
sa_l[1] <= wri_reg8:u_adr.data_out[1]
sa_l[2] <= wri_reg8:u_adr.data_out[2]
sa_l[3] <= wri_reg8:u_adr.data_out[3]
sa_l[4] <= wri_reg8:u_adr.data_out[4]
sa_l[5] <= wri_reg8:u_adr.data_out[5]
sa_l[6] <= wri_reg8:u_adr.data_out[6]
sa_l[7] <= wri_reg8:u_adr.data_out[7]
conn_on <= wri_reg8:u_a3_reg.data_out[0]
open_door <= wri_reg8:u_a3_reg.data_out[1]
allow <= wri_reg8:u_a3_reg.data_out[2]
fight <= wri_reg8:u_a3_reg.data_out[3]
torpedo_on <= wri_reg8:u_a3_reg.data_out[4]
pesudo_LED <= wri_reg8:u_reg_led.data_out[0]
run_led <= wri_reg8:u_reg_led.data_out[1]
rio_led <= wri_reg8:u_reg_led.data_out[2]
ad_led <= wri_reg8:u_reg_led.data_out[3]
cpu_led <= wri_reg8:u_reg_led.data_out[4]
tube <= wri_reg8:u_y7b_reg.data_out[0]
naborne <= wri_reg8:u_y7b_reg.data_out[1]
paborne <= wri_reg8:u_y7b_reg.data_out[2]
gulock <= wri_reg8:u_y7b_reg.data_out[3]
cmdr <= wri_reg8:u_y7b_reg.data_out[4]
sddr <= wri_reg8:u_y7b_reg.data_out[5]
cm_err_code[0] <= t_err_cm_code[4].DB_MAX_OUTPUT_PORT_TYPE
cm_err_code[1] <= t_err_cm_code[5].DB_MAX_OUTPUT_PORT_TYPE
cm_err_code[2] <= t_err_cm_code[6].DB_MAX_OUTPUT_PORT_TYPE
cm_err_code[3] <= t_err_cm_code[7].DB_MAX_OUTPUT_PORT_TYPE
sd_err_code[0] <= t_err_sd_code[0].DB_MAX_OUTPUT_PORT_TYPE
sd_err_code[1] <= t_err_sd_code[1].DB_MAX_OUTPUT_PORT_TYPE
sd_err_code[2] <= t_err_sd_code[2].DB_MAX_OUTPUT_PORT_TYPE
sd_err_code[3] <= t_err_sd_code[3].DB_MAX_OUTPUT_PORT_TYPE
tc <= t_err_cm_code[3].DB_MAX_OUTPUT_PORT_TYPE
y7b_err_led <= t_err_cm_code[0].DB_MAX_OUTPUT_PORT_TYPE
y7b_put_led <= t_err_cm_code[1].DB_MAX_OUTPUT_PORT_TYPE
y7b_ready_led <= t_err_cm_code[2].DB_MAX_OUTPUT_PORT_TYPE
flash_mode_led <= flash_mode_led~reg0.DB_MAX_OUTPUT_PORT_TYPE
rst_flash_mode_led => process2~0.IN1
flash_ready_led <= flash_ready_led~reg0.DB_MAX_OUTPUT_PORT_TYPE
XT <= XT~reg0.DB_MAX_OUTPUT_PORT_TYPE
XT_MODE <= t_err_sd_code[7].DB_MAX_OUTPUT_PORT_TYPE


|cpu|write_reg:u_read_write|wri_reg8:u_adr
iow => data_out[6]~reg0.CLK
iow => data_out[5]~reg0.CLK
iow => data_out[4]~reg0.CLK
iow => data_out[3]~reg0.CLK
iow => data_out[2]~reg0.CLK
iow => data_out[1]~reg0.CLK
iow => data_out[0]~reg0.CLK
iow => data_out[7]~reg0.CLK
rst => data_out[6]~reg0.ACLR
rst => data_out[5]~reg0.ACLR
rst => data_out[4]~reg0.ACLR
rst => data_out[3]~reg0.ACLR
rst => data_out[2]~reg0.ACLR
rst => data_out[1]~reg0.ACLR
rst => data_out[0]~reg0.ACLR
rst => data_out[7]~reg0.ACLR
cs => data_out[6]~reg0.ENA
cs => data_out[5]~reg0.ENA
cs => data_out[4]~reg0.ENA
cs => data_out[3]~reg0.ENA
cs => data_out[2]~reg0.ENA
cs => data_out[1]~reg0.ENA
cs => data_out[0]~reg0.ENA
cs => data_out[7]~reg0.ENA
data_in[0] => data_out[0]~reg0.DATAIN
data_in[1] => data_out[1]~reg0.DATAIN
data_in[2] => data_out[2]~reg0.DATAIN
data_in[3] => data_out[3]~reg0.DATAIN
data_in[4] => data_out[4]~reg0.DATAIN
data_in[5] => data_out[5]~reg0.DATAIN
data_in[6] => data_out[6]~reg0.DATAIN
data_in[7] => data_out[7]~reg0.DATAIN
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|cpu|write_reg:u_read_write|wri_reg8:u_reg_led
iow => data_out[6]~reg0.CLK
iow => data_out[5]~reg0.CLK
iow => data_out[4]~reg0.CLK
iow => data_out[3]~reg0.CLK
iow => data_out[2]~reg0.CLK
iow => data_out[1]~reg0.CLK
iow => data_out[0]~reg0.CLK
iow => data_out[7]~reg0.CLK
rst => data_out[6]~reg0.ACLR
rst => data_out[5]~reg0.ACLR
rst => data_out[4]~reg0.ACLR
rst => data_out[3]~reg0.ACLR
rst => data_out[2]~reg0.ACLR
rst => data_out[1]~reg0.ACLR
rst => data_out[0]~reg0.ACLR
rst => data_out[7]~reg0.ACLR
cs => data_out[6]~reg0.ENA
cs => data_out[5]~reg0.ENA
cs => data_out[4]~reg0.ENA
cs => data_out[3]~reg0.ENA
cs => data_out[2]~reg0.ENA
cs => data_out[1]~reg0.ENA
cs => data_out[0]~reg0.ENA
cs => data_out[7]~reg0.ENA
data_in[0] => data_out[0]~reg0.DATAIN
data_in[1] => data_out[1]~reg0.DATAIN
data_in[2] => data_out[2]~reg0.DATAIN
data_in[3] => data_out[3]~reg0.DATAIN
data_in[4] => data_out[4]~reg0.DATAIN
data_in[5] => data_out[5]~reg0.DATAIN
data_in[6] => data_out[6]~reg0.DATAIN
data_in[7] => data_out[7]~reg0.DATAIN
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|cpu|write_reg:u_read_write|wri_reg8:u_y7b_reg
iow => data_out[6]~reg0.CLK
iow => data_out[5]~reg0.CLK
iow => data_out[4]~reg0.CLK
iow => data_out[3]~reg0.CLK
iow => data_out[2]~reg0.CLK
iow => data_out[1]~reg0.CLK
iow => data_out[0]~reg0.CLK
iow => data_out[7]~reg0.CLK
rst => data_out[6]~reg0.ACLR
rst => data_out[5]~reg0.ACLR
rst => data_out[4]~reg0.ACLR
rst => data_out[3]~reg0.ACLR
rst => data_out[2]~reg0.ACLR
rst => data_out[1]~reg0.ACLR
rst => data_out[0]~reg0.ACLR
rst => data_out[7]~reg0.ACLR
cs => data_out[6]~reg0.ENA
cs => data_out[5]~reg0.ENA
cs => data_out[4]~reg0.ENA
cs => data_out[3]~reg0.ENA
cs => data_out[2]~reg0.ENA
cs => data_out[1]~reg0.ENA
cs => data_out[0]~reg0.ENA
cs => data_out[7]~reg0.ENA
data_in[0] => data_out[0]~reg0.DATAIN
data_in[1] => data_out[1]~reg0.DATAIN
data_in[2] => data_out[2]~reg0.DATAIN
data_in[3] => data_out[3]~reg0.DATAIN
data_in[4] => data_out[4]~reg0.DATAIN
data_in[5] => data_out[5]~reg0.DATAIN
data_in[6] => data_out[6]~reg0.DATAIN
data_in[7] => data_out[7]~reg0.DATAIN
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|cpu|write_reg:u_read_write|wri_reg8:u_a3_reg
iow => data_out[6]~reg0.CLK
iow => data_out[5]~reg0.CLK
iow => data_out[4]~reg0.CLK