--功能：讀出AD值.
--輸入：sa=x"c001"
--      啟動(dòng)命令：x"01" = 單獨(dú)啟動(dòng)CH指定的一路。
--              : x"03" = 從ch=0開(kāi)始連續(xù)啟動(dòng)3路。
--              " x"07" = 從ch=0開(kāi)始連續(xù)啟動(dòng)5路。           
--	  	sa=x"c000" 通道號(hào)：ch
--
--輸出：如果是測(cè)+5V參考電壓，則給出好與不好。
--	    如果是連通性檢查，則給出連通否。
--      如果是SD，則給出當(dāng)前SD位置。
--      如果是CM，則給出當(dāng)前CM位置。
--返回狀態(tài)：sa=x"c018"
--			adc_st=x"10"  正常結(jié)束。
--          adc_st="00"   復(fù)位 
--          adc_st=x"03"  AD未正常結(jié)束，超時(shí)。

LIBRARY IEEE;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity ad is port(
		rst				: in std_logic;
		sa				: in std_logic_vector(15 downto 0);
		sd_in			: in std_logic_vector(7 downto 0);
		iow				: in std_logic;
		ior				: in std_logic;
		p1mhz			: in std_logic;
		cda				: out std_logic_vector(2 downto 0);
		eoc_state		: in std_logic;
		sd				: in std_logic_vector(7 downto 0);
		rd_adl			: out std_logic;
		rd_adh			: out std_logic;
		start_ad 		: out std_logic;
	--ad 轉(zhuǎn)換狀態(tài)。00=轉(zhuǎn)換結(jié)束；11=轉(zhuǎn)換超時(shí)。	
		adc_state		: out std_logic_vector(7 downto 0);
		lchk_level 		: out std_logic_vector(1 downto 0); 
		p28v_level 		: out std_logic;
		n28v_level 		: out std_logic;
		ref5v_level		: out std_logic;	
		cm_level 		: out std_logic_vector(3 downto 0);
		sd_level		: out std_logic_vector(3 downto 0)

);
end entity ;

architecture ad of ad is

component wri_reg8 is port(
		iow			: in std_logic;
		rst			: in std_logic;
		cs			: in std_logic;
		data_in		: in std_logic_vector(7 downto 0);
		data_out	: out std_logic_vector(7 downto 0)
		);
end component;
		
	
signal st : integer range 0 to 31;
		
constant st_idle 			: integer	:= 0;
constant st_start_ad 		: integer	:= 1;	
constant st_ad_wait			: integer	:= 2;
constant st_ad_wait0		: integer	:= 3;
constant st_read_adl		: integer	:= 4;
constant st_read_adl_wait	: integer	:= 5;
constant st_read_adl_wait0	: integer	:= 6;
constant st_read_adh		: integer	:= 7;
constant st_read_adh_wait	: integer	:= 8;
constant st_read_adh_wait0	: integer	:= 9;
constant st_ad_next			: integer	:= 10;
constant st_ad_end			: integer	:= 11;
constant st_con_ad			: integer	:= 12;
constant st_ad_error		: integer	:= 13;
constant st_charge			: integer	:= 14;
constant st_cda_inc			: integer	:= 15;
constant st_cda_inc_wait	: integer	:= 16;
constant st_ad_end_wait		: integer	:= 17;

----lchk--如果小于clhk,則未開(kāi)鎖---
--未開(kāi)鎖時(shí)，輸入電壓3.75V，算作4V；開(kāi)鎖后，輸入電壓為4.7V
constant no_lock_l : std_logic_vector(11 downto 0) := x"a60";--3V
constant no_lock_h : std_logic_vector(11 downto 0) := x"b40";--4V
constant on_lock_l : std_logic_vector(11 downto 0) := x"B90";--4.5V
constant on_lock_h : std_logic_vector(11 downto 0) := x"c00";--5V

-------------cm1 data-----------------------
constant cml1 : std_logic_vector(11 downto 0) := x"920";
constant cmh1 : std_logic_vector(11 downto 0) := x"a00";
-------------cm2 data-----------------------
constant cml2 : std_logic_vector(11 downto 0) := x"a20";
constant cmh2 : std_logic_vector(11 downto 0) := x"b40";
-------------cm3 data-----------------------
constant cml3 : std_logic_vector(11 downto 0) := x"c00";
constant cmh3 : std_logic_vector(11 downto 0) := x"d00";
-------------cm4 data-----------------------
constant cml4 : std_logic_vector(11 downto 0) := x"e00";
constant cmh4 : std_logic_vector(11 downto 0) := x"f00";
-------------cm5 data-----------------------
constant cml5 : std_logic_vector(11 downto 0) := x"f20";
constant cmh5 : std_logic_vector(11 downto 0) := x"fff";
-------------cm6 data-----------------------
constant cml6 : std_logic_vector(11 downto 0) := x"520";
constant cmh6 : std_logic_vector(11 downto 0) := x"600";
-------------cm7 data-----------------------
constant cml7 : std_logic_vector(11 downto 0) := x"620";
constant cmh7 : std_logic_vector(11 downto 0) := x"700";
-------------cm8 data-----------------------
constant cml8 : std_logic_vector(11 downto 0) := x"420";
constant cmh8 : std_logic_vector(11 downto 0) := x"500";
-------------cm9 data-----------------------
constant cml9 : std_logic_vector(11 downto 0) := x"320";
constant cmh9 : std_logic_vector(11 downto 0) := x"400";
-------------cm1 data-----------------------
constant cml10 : std_logic_vector(11 downto 0) := x"220";
constant cmh10 : std_logic_vector(11 downto 0) := x"300";
-------------cm11 data-----------------------
constant cml11 : std_logic_vector(11 downto 0) := x"000";
constant cmh11 : std_logic_vector(11 downto 0) := x"100";
-------------cm1 data-----------------------
constant cml12 : std_logic_vector(11 downto 0) := x"120";
constant cmh12 : std_logic_vector(11 downto 0) := x"200";


-------------sd data----------------------- 
-------sd1---------
constant sdl1 : std_logic_vector(11 downto 0) := x"900";
constant sdh1 : std_logic_vector(11 downto 0) := x"9d0";
-------sd2---------
constant sdl2 : std_logic_vector(11 downto 0) := x"a00";
constant sdh2 : std_logic_vector(11 downto 0) := x"ad0";
-------sd3---------
constant sdl3 : std_logic_vector(11 downto 0) := x"b00";
constant sdh3 : std_logic_vector(11 downto 0) := x"bd0";
-------sd4----------
constant sdl4 : std_logic_vector(11 downto 0) := x"c00";
constant sdh4 : std_logic_vector(11 downto 0) := x"cd0";
-------sd5----------
constant sdl5 : std_logic_vector(11 downto 0) := x"d00";
constant sdh5 : std_logic_vector(11 downto 0) := x"dd0";
-------sd6----------
constant sdl6 : std_logic_vector(11 downto 0) := x"e00";
constant sdh6 : std_logic_vector(11 downto 0) := x"ed0";
-------sd7----------
constant sdl7 : std_logic_vector(11 downto 0) := x"f00";
constant sdh7 : std_logic_vector(11 downto 0) := x"fcc";

-----------ad_data_P28-------------
constant p28v_l : std_logic_vector(11 downto 0) := x"f90";
-----------ad_data_n28-------------
constant n28v_h : std_logic_vector(11 downto 0) := x"066";
-------------ref5v---------------
constant ref5v_l : std_logic_vector(11 downto 0) := x"B90";--4.5V
constant ref5v_h : std_logic_vector(11 downto 0) := x"c70";--5.5V


signal beg_ad,end_ad : std_logic;
--channel
signal cs_ch : std_logic;
signal t_cda : std_logic_vector(2 downto 0);
signal cda_inc : std_logic;
signal cs_com : std_logic;
signal com : std_logic_vector(7 downto 0);
signal ch_cnt : integer range 0 to 7;
signal ad_data_lchk : std_logic_vector(11 downto 0);
signal ad_data_sd : std_logic_vector(11 downto 0);
signal ad_data_cm : std_logic_vector(11 downto 0);
signal ad_data_P28 : std_logic_vector(11 downto 0);
signal ad_data_N28 : std_logic_vector(11 downto 0);
signal ad_data_V5 : std_logic_vector(11 downto 0);
signal ad_data_temp  : std_logic_vector(11 downto 0);
signal ad_charge_time : integer range 0 to 63;
signal ad_delay_time : integer range 0 to 110;
signal can_ad : std_logic;
signal t_adc_state : std_logic_vector(1 downto 0);
signal t_end_ad_tag : std_logic;
---------sig_ad data---------------------------
-----根據(jù)各個(gè)通道，判決輸入狀態(tài)。
--如果lchk_level="00",則+28VB未連接，
--    lchk_level="01",則未開(kāi)鎖。
--    lchk_level="10",則已開(kāi)鎖。
signal t_lchk_level : std_logic_vector(1 downto 0); 
--共1-7級(jí)
signal t_sd_level : std_logic_vector(3 downto 0);
--共1-12級(jí)
signal t_cm_level : std_logic_vector(3 downto 0);

--測(cè)p28v。經(jīng)變壓后成9.5V以上。
--如果電壓在9.5V，則p28_level='0',否則='1'.
signal t_p28v_level : std_logic;

--測(cè)n28v。經(jīng)變壓后成0.5V以下。
--如果電壓在0.5V以下，則n28_level='0',否則='1'.
signal t_n28v_level : std_logic;

--測(cè)ref5v。如果電壓在4.5V~5.5V，則ref5v_level='0',否則='1'。
signal t_ref5v_level : std_logic; 

begin



lchk_level <= t_lchk_level; 
p28v_level <= t_p28v_level;
n28v_level <= t_n28v_level;
ref5v_level <= t_ref5v_level;	
cm_level <= t_cm_level;
sd_level <= t_sd_level;	

generate_lchk_level : process(ad_data_lchk)
begin
	if ad_data_lchk < no_lock_l then
		t_lchk_level <= "00";
	elsif ad_data_lchk >= no_lock_l and ad_data_lchk <= no_lock_h then
		t_lchk_level <= "01";	 
	elsif ad_data_lchk >= on_lock_l and ad_data_lchk <= on_lock_h then
		t_lchk_level <= "10";	 	
	else
		t_lchk_level <= "00";	
	end if;	
end process;

gen_sd_level : process(ad_data_sd)
begin
	if ad_data_sd >= sdl1 and ad_data_sd <= sdh1 then
		t_sd_level <= x"1";
	elsif ad_data_sd >= sdl2 and ad_data_sd <= sdh2 then
		t_sd_level <= x"2";			  
	elsif ad_data_sd >= sdl3 and ad_data_sd <= sdh3 then
		t_sd_level <= x"3";			  
	elsif ad_data_sd >= sdl4 and ad_data_sd <= sdh4 then
		t_sd_level <= x"4";			  
	elsif ad_data_sd >= sdl5 and ad_data_sd <= sdh5 then
		t_sd_level <= x"5";			  
	elsif ad_data_sd >= sdl6 and ad_data_sd <= sdh6 then
		t_sd_level <= x"6";			  
	elsif ad_data_sd >= sdl7 and ad_data_sd <= sdh7 then
		t_sd_level <= x"7";			  
	else
		t_sd_level <= x"0";
	end if;	 		
end process;