?? seg47.fit.rpt
字號(hào):
; Perform Register Duplication ; Off ; Off ;
; Perform Register Retiming ; Off ; Off ;
; Perform Asynchronous Signal Pipelining ; Off ; Off ;
; Fitter Effort ; Auto Fit ; Auto Fit ;
; Physical Synthesis Effort Level ; Normal ; Normal ;
; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
; Auto Register Duplication ; Off ; Off ;
; Auto Global Clock ; On ; On ;
; Auto Global Register Control Signals ; On ; On ;
+------------------------------------------------------+--------------------------------+--------------------------------+
+--------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+---------------------+
; Option ; Setting ;
+----------------------------------------------+---------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Active Serial ;
; Error detection CRC ; Off ;
; Reserve all unused pins ; As input tri-stated ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+---------------------+
+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in F:/mywork/seg47/seg47.fit.eqn.
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in F:/mywork/seg47/seg47.pin.
+----------------------------------------------------------------------+
; Fitter Resource Usage Summary ;
+---------------------------------------------+------------------------+
; Resource ; Usage ;
+---------------------------------------------+------------------------+
; Total logic elements ; 67 / 5,980 ( 1 % ) ;
; -- Combinational with no register ; 19 ;
; -- Register only ; 0 ;
; -- Combinational with a register ; 48 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 15 ;
; -- 3 input functions ; 0 ;
; -- 2 input functions ; 48 ;
; -- 1 input functions ; 4 ;
; -- 0 input functions ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 24 ;
; -- arithmetic mode ; 43 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 0 ;
; -- asynchronous clear/load mode ; 18 ;
; ; ;
; Total LABs ; 7 / 598 ( 1 % ) ;
; Logic elements in carry chains ; 46 ;
; User inserted logic elements ; 0 ;
; Virtual pins ; 0 ;
; I/O pins ; 13 / 185 ( 7 % ) ;
; -- Clock pins ; 1 / 2 ( 50 % ) ;
; Global signals ; 5 ;
; M4Ks ; 0 / 20 ( 0 % ) ;
; Total memory bits ; 0 / 92,160 ( 0 % ) ;
; Total RAM block bits ; 0 / 92,160 ( 0 % ) ;
; PLLs ; 0 / 2 ( 0 % ) ;
; Global clocks ; 5 / 8 ( 63 % ) ;
; Maximum fan-out node ; clk ;
; Maximum fan-out ; 30 ;
; Highest non-global fan-out signal ; segmain:inst|comclk[0] ;
; Highest non-global fan-out ; 13 ;
; Total fan-out ; 261 ;
; Average fan-out ; 3.18 ;
+---------------------------------------------+------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; clk ; 28 ; 1 ; 0 ; 12 ; 2 ; 30 ; 0 ; yes ; no ; no ; no ; no ; Off ; LVTTL ; Off ; User ;
; reset ; 76 ; 4 ; 8 ; 0 ; 0 ; 18 ; 0 ; yes ; no ; no ; no ; no ; Off ; LVTTL ; Off ; User ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins ;
+-----------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ;
+-----------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------------+
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