library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity subcont is
 PORT( clk  :  IN  STD_LOGIC;
       rst  :  IN  STD_LOGIC;
       cont :  OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
     
 );
END subcont;
ARCHITECTURE behav OF subcont IS 
  SIGNAL time   :  STD_LOGIC_VECTOR(7 DOWNTO 0); 
begin
  process(rst,clk)
begin
 if rst='1' then
   time<="11111111";
  elsif rising_edge(clk) then
      time <=time-1;
      end if;
end process;
cont<=time;
end behav;