?? seg47.sim.rpt
字號:
; Total coverage as a percentage ; 33.04 % ;
; Total nodes checked ; 80 ;
; Total output ports checked ; 115 ;
; Total output ports with complete 1/0-value coverage ; 38 ;
; Total output ports with no 1/0-value coverage ; 76 ;
; Total output ports with no 1-value coverage ; 76 ;
; Total output ports with no 0-value coverage ; 77 ;
+-----------------------------------------------------+--------------+
The following table displays output ports that toggle between 1 and 0 during simulation.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage ;
+-----------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-----------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------+------------------+
; |seg47|segmain:inst|comclk[0] ; |seg47|segmain:inst|comclk[0] ; regout ;
; |seg47|segmain:inst|ledcom[3]~31 ; |seg47|segmain:inst|ledcom[3]~31 ; combout ;
; |seg47|rtl~2 ; |seg47|rtl~2 ; combout ;
; |seg47|rtl~34 ; |seg47|rtl~34 ; combout ;
; |seg47|rtl~35 ; |seg47|rtl~35 ; combout ;
; |seg47|segmain:inst|dataout[0]~70 ; |seg47|segmain:inst|dataout[0]~70 ; combout ;
; |seg47|segmain:inst|dataout[0]~71 ; |seg47|segmain:inst|dataout[0]~71 ; combout ;
; |seg47|segmain:inst|dataout[1]~72 ; |seg47|segmain:inst|dataout[1]~72 ; combout ;
; |seg47|segmain:inst|dataout[2]~74 ; |seg47|segmain:inst|dataout[2]~74 ; combout ;
; |seg47|segmain:inst|dataout[2]~75 ; |seg47|segmain:inst|dataout[2]~75 ; combout ;
; |seg47|segmain:inst|dataout[3]~76 ; |seg47|segmain:inst|dataout[3]~76 ; combout ;
; |seg47|segmain:inst|dataout[3]~77 ; |seg47|segmain:inst|dataout[3]~77 ; combout ;
; |seg47|bin27seg:inst1|data_out[6]~103 ; |seg47|bin27seg:inst1|data_out[6]~103 ; combout ;
; |seg47|bin27seg:inst1|data_out[5]~104 ; |seg47|bin27seg:inst1|data_out[5]~104 ; combout ;
; |seg47|bin27seg:inst1|data_out[2]~107 ; |seg47|bin27seg:inst1|data_out[2]~107 ; combout ;
; |seg47|bin27seg:inst1|data_out[1]~108 ; |seg47|bin27seg:inst1|data_out[1]~108 ; combout ;
; |seg47|bin27seg:inst1|data_out[0]~109 ; |seg47|bin27seg:inst1|data_out[0]~109 ; combout ;
; |seg47|lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_6gd:auto_generated|safe_q[2] ; |seg47|lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_6gd:auto_generated|safe_q[2] ; regout ;
; |seg47|lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_6gd:auto_generated|safe_q[2] ; |seg47|lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_6gd:auto_generated|counter_cella2~COUT ; cout0 ;
; |seg47|lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_6gd:auto_generated|safe_q[2] ; |seg47|lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_6gd:auto_generated|counter_cella2~COUTCOUT1_1 ; cout1 ;
; |seg47|lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_6gd:auto_generated|safe_q[1] ; |seg47|lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_6gd:auto_generated|counter_cella1~COUT ; cout0 ;
; |seg47|lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_6gd:auto_generated|safe_q[1] ; |seg47|lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_6gd:auto_generated|counter_cella1~COUTCOUT1_1 ; cout1 ;
; |seg47|lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_6gd:auto_generated|safe_q[0] ; |seg47|lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_6gd:auto_generated|counter_cella0~COUT ; cout0 ;
; |seg47|lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_6gd:auto_generated|safe_q[0] ; |seg47|lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_6gd:auto_generated|counter_cella0~COUTCOUT1_1 ; cout1 ;
; |seg47|lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_6gd:auto_generated|safe_q[5] ; |seg47|lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_6gd:auto_generated|counter_cella5~COUTCOUT1_1 ; cout1 ;
; |seg47|lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_6gd:auto_generated|safe_q[4] ; |seg47|lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_6gd:auto_generated|counter_cella4~COUT ; cout ;
; |seg47|lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_6gd:auto_generated|safe_q[3] ; |seg47|lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_6gd:auto_generated|counter_cella3~COUT ; cout0 ;
; |seg47|lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_6gd:auto_generated|safe_q[3] ; |seg47|lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_6gd:auto_generated|counter_cella3~COUTCOUT1_1 ; cout1 ;
; |seg47|clk ; |seg47|clk ; combout ;
; |seg47|ledcom[3] ; |seg47|ledcom[3] ; padio ;
; |seg47|ledcom[2] ; |seg47|ledcom[2] ; padio ;
; |seg47|ledcom[1] ; |seg47|ledcom[1] ; padio ;
; |seg47|ledcom[0] ; |seg47|ledcom[0] ; padio ;
; |seg47|seg7[6] ; |seg47|seg7[6] ; padio ;
; |seg47|seg7[5] ; |seg47|seg7[5] ; padio ;
; |seg47|seg7[2] ; |seg47|seg7[2] ; padio ;
; |seg47|seg7[1] ; |seg47|seg7[1] ; padio ;
; |seg47|seg7[0] ; |seg47|seg7[0] ; padio ;
+-----------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 1 during simulation.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage ;
+------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------+
; |seg47|addcont:inst3|time[0] ; |seg47|addcont:inst3|time[0]~57 ; cout0 ;
; |seg47|addcont:inst3|time[0] ; |seg47|addcont:inst3|time[0]~57COUT1_89 ; cout1 ;
; |seg47|addcont:inst3|time[4] ; |seg47|addcont:inst3|time[4]~61 ; cout ;
; |seg47|subcont:inst4|time[4] ; |seg47|subcont:inst4|time[4]~57 ; cout ;
; |seg47|subcont:inst4|time[0] ; |seg47|subcont:inst4|time[0]~61 ; cout0 ;
; |seg47|subcont:inst4|time[0] ; |seg47|subcont:inst4|time[0]~61COUT1_89 ; cout1 ;
; |seg47|subcont:inst4|time[5] ; |seg47|subcont:inst4|time[5]~65 ; cout0 ;
; |seg47|subcont:inst4|time[5] ; |seg47|subcont:inst4|time[5]~65COUT1_92 ; cout1 ;
; |seg47|addcont:inst3|time[5] ; |seg47|addcont:inst3|time[5]~65 ; cout0 ;
; |seg47|addcont:inst3|time[5] ; |seg47|addcont:inst3|time[5]~65COUT1_92 ; cout1 ;
; |seg47|addcont:inst3|time[1] ; |seg47|addcont:inst3|time[1]~69 ; cout0 ;
; |seg47|addcont:inst3|time[1] ; |seg47|addcont:inst3|time[1]~69COUT1_90 ; cout1 ;
; |seg47|subcont:inst4|time[1] ; |seg47|subcont:inst4|time[1]~69 ; cout0 ;
; |seg47|subcont:inst4|time[1] ; |seg47|subcont:inst4|time[1]~69COUT1_90 ; cout1 ;
; |seg47|segmain:inst|dataout[1]~73 ; |seg47|segmain:inst|dataout[1]~73 ; combout ;
; |seg47|addcont:inst3|time[2] ; |seg47|addcont:inst3|time[2]~73 ; cout0 ;
; |seg47|addcont:inst3|time[2] ; |seg47|addcont:inst3|time[2]~73COUT1_91 ; cout1 ;
; |seg47|addcont:inst3|time[6] ; |seg47|addcont:inst3|time[6]~77 ; cout0 ;
; |seg47|addcont:inst3|time[6] ; |seg47|addcont:inst3|time[6]~77COUT1_93 ; cout1 ;
; |seg47|subcont:inst4|time[6] ; |seg47|subcont:inst4|time[6]~73 ; cout0 ;
; |seg47|subcont:inst4|time[6] ; |seg47|subcont:inst4|time[6]~73COUT1_93 ; cout1 ;
; |seg47|subcont:inst4|time[2] ; |seg47|subcont:inst4|time[2]~77 ; cout0 ;
; |seg47|subcont:inst4|time[2] ; |seg47|subcont:inst4|time[2]~77COUT1_91 ; cout1 ;
; |seg47|addcont:inst3|time[3] ; |seg47|addcont:inst3|time[3]~81 ; cout0 ;
; |seg47|addcont:inst3|time[3] ; |seg47|addcont:inst3|time[3]~81COUT1 ; cout1 ;
; |seg47|subcont:inst4|time[3] ; |seg47|subcont:inst4|time[3]~85 ; cout0 ;
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