`timescale 1ns / 1ps////////////////////////////////////////////////////////////////////////////////// Company: // Engineer://// Create Date:    07:57:25 01/12/07// Design Name:    Angela// Module Name:    request// Project Name:   // Target Device:  // Tool versions:  // Description://// Dependencies:// // Revision:// Revision 0.01 - File Created// Additional Comments:// ////////////////////////////////////////////////////////////////////////////////module request(clk, reset, drive_1, drive_2, load_enable_low,load_enable_high, floor_1, floor_2, req_clr_1, req_clr_2, req_in_0, req_in_1, req_in_2, req_in_3, req_in_4, req_in_5, req_in_6, req_in_7, req_out_1, req_out_2, r_up_1,r_up_2, r_down_1, r_down_2);parameter width = 2;    input clk;    input reset; //	 input inc_1;	  ////	 input inc_2;	 input drive_1;     //驅動信號到來時計算是否有上些請求	 input drive_2;    input [2:0] floor_1;	 input [2:0] floor_2;    input [width-1:0] req_in_0;	//eight input	 input [width-1:0] req_in_1;	 input [width-1:0] req_in_2;	 input [width-1:0] req_in_3;	 input [width-1:0] req_in_4;	 input [width-1:0] req_in_5;	 input [width-1:0] req_in_6;	 input [width-1:0] req_in_7;	 input [1:0] req_clr_1;	 input [1:0] req_clr_2;	 input load_enable_low,load_enable_high;     output [width-1:0] req_out_1;	reg [width-1:0] req_out_1;	 output [width-1:0] req_out_2;   reg [width-1:0] req_out_2;	 output r_up_1; reg r_up_1;	 output r_up_2; reg r_up_2;	 output r_down_1; reg r_down_1;	 output r_down_2; reg r_down_2;	 	 integer i = 0;	 reg [width-1:0] register [7:0];	 reg tem;	 always @(posedge clk or negedge reset)	 	 begin 	 	 if(!reset) begin	 	for (i = 0 ; i <= 7; i = i+1)			register[i] <= 'b0;		tem <= 'b0;					end	 else //	 	begin		if(load_enable_low)				begin			   register[0] <= register[0] | req_in_0;		 		register[1] <= register[1] | req_in_1;		 		register[2] <= register[2] | req_in_2;		 		register[3] <= register[3] | req_in_3; 				end  	 		 else if(load_enable_high)				begin		 		register[4] <= register[4] | req_in_4;				 		register[5] <= register[5] | req_in_5;		 		register[6] <= register[6] | req_in_6;		 		register[7] <= register[7] | req_in_7;	 				end  	       else//		 if(req_clr_1 || req_clr_2)        begin		  case(req_clr_1 )//| req_clr_2)		   'b01:			   begin		           		 case (floor_1)            		 'b000:	if(register[0])   register[0][0] <= 'b0;// register[0] <= register[0] - req_clr_1;            		 'b001:	if(register[1])   register[1][0] <= 'b0;// register[1] <= register[1] - req_clr_1;            		 'b010:	if(register[2])   register[2][0] <= 'b0;// register[2] <= register[2] - req_clr_1;            		 'b011:	if(register[3])   register[3][0] <= 'b0;// register[3] <= register[3] - req_clr_1;            		 'b100:	if(register[4])   register[4][0] <= 'b0;// register[4] <= register[4] - req_clr_1;            		 'b101:	if(register[5])   register[5][0] <= 'b0;// register[5] <= register[5] - req_clr_1;             		 'b110:	if(register[6])   register[6][0] <= 'b0;// register[6] <= register[6] - req_clr_1;             		 'b111:	if(register[7])   register[7][0] <= 'b0;// register[7] <= register[7] - req_clr_1;		          endcase				end			 'b10:			    begin				    case(floor_1)			 			'b000:	if(register[0])   register[0][1] <= 'b0;   // register[0] <= register[0] - req_clr_2;   		         'b001:	if(register[1])   register[1][1] <= 'b0;   // register[1] <= register[1] - req_clr_2;	    	 			'b010:	if(register[2])   register[2][1] <= 'b0;   // register[2] <= register[2] - req_clr_2;    		 			'b011:	if(register[3])   register[3][1] <= 'b0;   // register[3] <= register[3] - req_clr_2;    		 			'b100:	if(register[4])   register[4][1] <= 'b0;   // register[4] <= register[4] - req_clr_2;    		 			'b101:	if(register[5])   register[5][1] <= 'b0;   // register[5] <= register[5] - req_clr_2;     		 			'b110:	if(register[6])   register[6][1] <= 'b0;   // register[6] <= register[6] - req_clr_2;	     	 			'b111:	if(register[7])   register[7][1] <= 'b0;   // register[7] <= register[7] - req_clr_2;				    endcase				 end/*			 'b11:				    begin				    case(floor_1)			 			'b000:	if(register[0])   register[0] <= 'b00;   // register[0] <= register[0] - req_clr_2;   		         'b001:	if(register[1])   register[1] <= 'b00;   // register[1] <= register[1] - req_clr_2;	    	 			'b010:	if(register[2])   register[2] <= 'b00;   // register[2] <= register[2] - req_clr_2;    		 			'b011:	if(register[3])   register[3] <= 'b00;   // register[3] <= register[3] - req_clr_2;    		 			'b100:	if(register[4])   register[4] <= 'b00;  // register[4] <= register[4] - req_clr_2;    		 			'b101:	if(register[5])   register[5] <= 'b00;   // register[5] <= register[5] - req_clr_2;     		 			'b110:	if(register[6])   register[6] <= 'b00;   // register[6] <= register[6] - req_clr_2;	     	 			'b111:	if(register[7])   register[7] <= 'b00;   // register[7] <= register[7] - req_clr_2;				    endcase				 end	*/		   			  default:			     begin				   /*					   	 register[0][0] <= register[0][0];							 register[1][0] <= register[1][0];							 register[2][0] <= register[2][0];							 register[3][0] <= register[3][0];							 register[4][0] <= register[4][0];							 register[5][0] <= register[5][0];							 register[6][0] <= register[6][0];					   	 register[7][0] <= register[7][0];	 */							 tem <= 'b1;				  end	 		   endcase		  case(req_clr_2 )//| req_clr_2)		   'b01:			   begin		           		 case (floor_2)            		 'b000:	if(register[0])   register[0][0] <= 'b0;// register[0] <= register[0] - req_clr_1;            		 'b001:	if(register[1])   register[1][0] <= 'b0;// register[1] <= register[1] - req_clr_1;            		 'b010:	if(register[2])   register[2][0] <= 'b0;// register[2] <= register[2] - req_clr_1;            		 'b011:	if(register[3])   register[3][0] <= 'b0;// register[3] <= register[3] - req_clr_1;            		 'b100:	if(register[4])   register[4][0] <= 'b0;// register[4] <= register[4] - req_clr_1;            		 'b101:	if(register[5])   register[5][0] <= 'b0;// register[5] <= register[5] - req_clr_1;             		 'b110:	if(register[6])   register[6][0] <= 'b0;// register[6] <= register[6] - req_clr_1;             		 'b111:	if(register[7])   register[7][0] <= 'b0;// register[7] <= register[7] - req_clr_1;		          endcase				end			 'b10:			    begin				    case(floor_2)			 			'b000:	if(register[0])   register[0][1] <= 'b0;   // register[0] <= register[0] - req_clr_2;   		         'b001:	if(register[1])   register[1][1] <= 'b0;   // register[1] <= register[1] - req_clr_2;	    	 			'b010:	if(register[2])   register[2][1] <= 'b0;   // register[2] <= register[2] - req_clr_2;    		 			'b011:	if(register[3])   register[3][1] <= 'b0;   // register[3] <= register[3] - req_clr_2;    		 			'b100:	if(register[4])   register[4][1] <= 'b0;   // register[4] <= register[4] - req_clr_2;    		 			'b101:	if(register[5])   register[5][1] <= 'b0;   // register[5] <= register[5] - req_clr_2;     		 			'b110:	if(register[6])   register[6][1] <= 'b0;   // register[6] <= register[6] - req_clr_2;	     	 			'b111:	if(register[7])   register[7][1] <= 'b0;   // register[7] <= register[7] - req_clr_2;				    endcase				 end/*			 'b11:				    begin				    case(floor_1)			 			'b000:	if(register[0])   register[0] <= 'b00;   // register[0] <= register[0] - req_clr_2;   		         'b001:	if(register[1])   register[1] <= 'b00;   // register[1] <= register[1] - req_clr_2;	    	 			'b010:	if(register[2])   register[2] <= 'b00;   // register[2] <= register[2] - req_clr_2;    		 			'b011:	if(register[3])   register[3] <= 'b00;   // register[3] <= register[3] - req_clr_2;    		 			'b100:	if(register[4])   register[4] <= 'b00;  // register[4] <= register[4] - req_clr_2;    		 			'b101:	if(register[5])   register[5] <= 'b00;   // register[5] <= register[5] - req_clr_2;     		 			'b110:	if(register[6])   register[6] <= 'b00;   // register[6] <= register[6] - req_clr_2;	     	 			'b111:	if(register[7])   register[7] <= 'b00;   // register[7] <= register[7] - req_clr_2;				    endcase				 end	*/		   			  default:			     begin				   /*					   	 register[0][1] <= register[0][1];    						 register[1][1] <= register[1][1];							 register[2][1] <= register[2][1];							 register[3][1] <= register[3][1];							 register[4][1] <= register[4][1];							 register[5][1] <= register[5][1];							 register[6][1] <= register[6][1];					   	 register[7][1] <= register[7][1];	*/							 tem <= 'b1;				  end	 		   endcase		 end/*	  else		     begin				   					   	 register[0] <= register[0];							 register[1] <= register[1];							 register[2] <= register[2];							 register[3] <= register[3];							 register[4] <= register[4];							 register[5] <= register[5];							 register[6] <= register[6];					   	 register[7] <= register[7];				  end	  		  */		//		req_clr_1 = 'b00;//		req_clr_2 = 'b00;  		 		//	end		      			end	always @(posedge drive_1)	begin		r_up_1 = 0;		r_down_1 = 0;	 		case(floor_1)	//是否在某曾有請求		 'b000: begin		 			req_out_1 <= register[0];					if(register[1] || register[2] || register[3] || register[4] || register[5] || register[6] || register[7])					     r_up_1 = 1; 					else r_up_1 = 0;					r_down_1 = 0;						end								 'b001: begin		 			req_out_1 <= register[1];					if(register[2] || register[3] || register[4] || register[5] || register[6] || register[7])						r_up_1 = 1; 					else r_up_1 = 0;					if(register[0])						begin r_down_1 = 1; end					else r_down_1 = 0;				  end						 'b010:  begin		 			req_out_1 <= register[2];					if(register[3] || register[4] || register[5] || register[6] || register[7])						begin r_up_1 = 1; end					else r_up_1 = 0;					if(register[0] || register[1])						begin r_down_1 = 1; end					else r_down_1 = 0;				  end		 'b011:  begin		 			req_out_1 <= register[3];					if(register[4] || register[5] || register[6] || register[7])						begin r_up_1 = 1; end					else r_up_1 = 0;					if(register[0] || register[1] || register[2])						begin r_down_1 = 1; end					else r_down_1 = 0;				  end		 'b100: begin		 			req_out_1 <= register[4];					if(register[5] || register[6] || register[7])						begin r_up_1 = 1; end					else r_up_1 = 0;					if(register[0] || register[2] || register[3] ||register[1])						begin r_down_1 = 1; end					else r_down_1 = 0;				  end				 'b101: begin		 			req_out_1 <= register[5];					if( register[6] || register[7])						begin r_up_1 = 1; end					else r_up_1 = 0;					if(register[0] || register[2] || register[3] ||register[4] ||register[1])						begin r_down_1 = 1; end					else r_down_1 = 0;				  end				 'b110: begin		 			req_out_1 <= register[6];					if( register[7])						begin r_up_1 = 1; end					else r_up_1 = 0;					if(register[0] || register[2] || register[3] ||register[4] ||register[5] || register[1] )						begin r_down_1 = 1; end					else r_down_1 = 0;				  end				 'b111: begin		 			req_out_1 <= register[7];					r_up_1 = 0;					if(register[0] || register[2] || register[3] ||register[4] ||register[5] || register[6] ||register[1] )						begin r_down_1 = 1; end					else r_down_1 = 0;				  end				endcase	end	always @(posedge drive_2)	begin		r_up_2 = 0;		r_down_2 = 0;	 		case(floor_2)	//是否在某曾有請求		 'b000: begin		 			req_out_2 <= register[0];					if(register[1] || register[2] || register[3] || register[4] || register[5] || register[6] || register[7])					     r_up_2 = 1; 					else r_up_2 = 0;					r_down_2 = 0;						end			 'b001: begin		 			req_out_2 <= register[1];					if(register[2] || register[3] || register[4] || register[5] || register[6] || register[7])						r_up_2 = 1; 					else r_up_2 = 0;					if(register[0])						begin r_down_2 = 1; end					else r_down_2 = 0;				  end						 'b010:  begin		 			req_out_2 <= register[2];					if(register[3] || register[4] || register[5] || register[6] || register[7])						begin r_up_2 = 1; end					else r_up_2 = 0;					if(register[0] || register[1])						begin r_down_2 = 1; end					else r_down_2 = 0;				  end		 'b011:  begin		 			req_out_2 <= register[3];					if(register[4] || register[5] || register[6] || register[7])						begin r_up_2 = 1; end					else r_up_2 = 0;					if(register[0] || register[1] || register[2])						begin r_down_2 = 1; end					else r_down_2 = 0;				  end		 'b100: begin		 			req_out_2 <= register[4];					if(register[5] || register[6] || register[7])						begin r_up_2 = 1; end					else r_up_2 = 0;					if(register[0] || register[2] || register[3] ||register[1])						begin r_down_2 = 1; end					else r_down_2 = 0;				  end				 'b101: begin		 			req_out_2 <= register[5];					if( register[6] || register[7])						begin r_up_2 = 1; end					else r_up_2 = 0;					if(register[0] || register[2] || register[3] ||register[4] ||register[1])						begin r_down_2 = 1; end					else r_down_2 = 0;				  end				 'b110: begin		 			req_out_2 <= register[6];					if( register[7])						begin r_up_2 = 1; end					else r_up_2 = 0;					if(register[0] || register[2] || register[3] ||register[4] ||register[5] || register[1] )						begin r_down_2 = 1; end					else r_down_2 = 0;				  end				 'b111: begin		 			req_out_2 <= register[7];					r_up_2 = 0;					if(register[0] || register[2] || register[3] ||register[4] ||register[5] || register[6] ||register[1] )						begin r_down_2 = 1; end					else r_down_2 = 0;				  end				endcase	endendmodule