`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    22:16:32 01/15/07
// Design Name:    
// Module Name:    tt
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module tt(load_enable, register_in_0, register_in_1, register_in_2, register_in_3, 
          register_in_4, register_in_5, register_in_6, register_in_7, register_out,
           reset, request, floor,des_clr,clk,up,down,now);
								  
  parameter width = 8;

    input register_in_0;
    input register_in_1;
    input register_in_2;
    input register_in_3;
    input register_in_4;
    input register_in_5;
    input register_in_6;
    input register_in_7;
    input load_enable;
	 input [2:0] floor;
    input des_clr;  
	 input clk;
	 input reset;
	 input request;
	 
    output [width-1:0] register_out;

	 reg [width-1:0] register_out;

	 output up; reg up;
	 output down; reg down;
	 output now; reg now;

	 always @ (posedge clk or negedge reset)
	   begin
		   if(!reset)
			    register_out <= 8'b00000000;
			else
			    begin
				    if(load_enable)
					     begin 
						     register_out[0] <= register_in_0;
							  register_out[1] <= register_in_1;
							  register_out[2] <= register_in_2;
							  register_out[3] <= register_in_3;
							  register_out[4] <= register_in_4;
							  register_out[5] <= register_in_5;
							  register_out[6] <= register_in_6;
							  register_out[7] <= register_in_7;
						  end


					  else 				
 	  		      	if(des_clr)
	        			begin
	         		case(floor)
					'b000:  begin
								register_out[0] <= 0;

							  end
					'b001:  begin									
								register_out[1] <= 0;

							  end
					'b010:  begin
								register_out[2] <= 0;

							  end
					'b011:  begin
								register_out[3] <= 0;

				  			  end
					'b100:  begin
								register_out[4] <= 0;

			    			  end
					'b101:  begin
								register_out[5] <= 0;

							  end
					'b110:  begin
								register_out[6] <= 0;

			   			  end
					'b111:  begin					
								register_out[7] <= 0;

					    	  end
				endcase
				end		
					  else	
					     begin
						     register_out[0] <= register_out[0];
							  register_out[1] <= register_out[1];
							  register_out[2] <= register_out[2];
							  register_out[3] <= register_out[3];
							  register_out[4] <= register_out[4];
							  register_out[5] <= register_out[5];
							  register_out[6] <= register_out[6];
							  register_out[7] <= register_out[7];						    
						  end
						  

				 end   
		end


			
      always @ (posedge request)//buffer 不能加進去
		begin
			case (floor)
			'b000:  begin	
						down = 0;  //第一層的向下信號一定為零
																		 
			 			if (register_out[0])
							now = 1;
						else now = 0;
			
						if(register_out[7:1])
							up = 1;
						else 	up = 0;
			

						end
			'b001:  	 begin
									if (register_out[1])
										now = 1;
									else now = 0;
			
									if(register_out[7:2])
										up = 1;
									else 	up = 0;
			
									if(register_out[0])
										down = 1;
									else  down = 0; 
								  end

			'b010:  	 begin
									if (register_out[2])
										now = 1;
									else now = 0;
			
									if(register_out[7:2])
										up = 1;
									else 	up = 0;
			
									if(register_out[1:0])
										down = 1;
									else  down = 0; 
								  end
			'b011:  	   begin
									if (register_out[3])
										now = 1;
									else now = 0;
			
									if(register_out[7:4])
										up = 1;
									else 	up = 0;
			
									if(register_out[2:0])
										down = 1;
									else  down = 0; 
								  end
			'b100:  	 	 begin
									if (register_out[4])
										now = 1;
									else now = 0;
			
									if(register_out[7:5])
										up = 1;
									else 	up = 0;
			
									if(register_out[3:0])
										down = 1;
									else  down = 0; 
								  end
			'b101:  	   begin
									if (register_out[5])
										now = 1;
									else now = 0;
			
									if(register_out[7:6])
										up = 1;
									else 	up = 0;
			
									if(register_out[4:0])
										down = 1;
									else  down = 0; 
								  end

			'b110:    begin
									if (register_out[6])
										now = 1;
									else now = 0;
			
									if(register_out[7])
										up = 1;
									else 	up = 0;
			
									if(register_out[5:0])
										down = 1;
									else  down = 0; 
								  end

			'b111:  	 begin
									if (register_out[7])
										now = 1;
									else now = 0;
			
								 	up = 0; //頂層肯定沒有向上請求
			
									if(register_out[6:0])
										down = 1;
									else  down = 0; 
					    end
			endcase

    end

endmodule