`timescale 1ns / 1ps////////////////////////////////////////////////////////////////////////////////// Company: // Engineer://// Create Date:    12:35:21 01/12/07// Design Name:    // Module Name:    g_ele// Project Name:   // Target Device:  // Tool versions:  // Description://// Dependencies:// // Revision:// Revision 0.01 - File Created// Additional Comments:// ////////////////////////////////////////////////////////////////////////////////module g_ele(clk,reset,re_in, des_req,code,             open_1,open_2,close_1,close_2,load_enable,floor_1,				 floor_2,run_state_1,run_state_2,				 d_floor_1,d_floor_2);	 input clk;	 input reset;	 input re_in;	 input [7:0] des_req;	 input [1:0] code;	 input open_1;			  //open manhand	 input open_2;	 input close_1;		  //close manhand	 input close_2;	 input load_enable;  //requeset  的使能信號	 output [2:0] floor_1;    //電梯運行到哪一層	 output [2:0] floor_2;	 output [1:0] run_state_1;    //電梯運行的狀態(tài)。	up or down?	 output [1:0] run_state_2;	 output [7:0] d_floor_1;        //顯示內(nèi)部請求	 output [7:0] d_floor_2;//module cu_two(stat_1, stat_2, mov_1, mov_2, ch_stat_1, ch_stat_2, //req_clr_1,req_clr_2,des_1,des_2, req_1, req_2, up_1, up_2,//down_1, down_2, now_1, now_2,stop_1,stop_2,sel_1, sel_2);																 	 //cu_two    wire [1:0] req_out_1;//本層外部請求    wire [1:0] req_out_2;     wire up_1;   	//上有目的或請求	 After total....	 wire up_2;    wire down_1;	//本層之下有同	 wire down_2;	 wire now_1;		//	目的	 wire now_2;//	 wire [1:0] sel;  //select request from 1 and 2 	 wire [1:0] mov_1;  //reg [1:0] mov_1;    wire [1:0] mov_2;	//reg [1:0] mov_2;	 wire stop_1;	 //reg stop_1;	 wire stop_2;	 //reg stop_2;    wire [1:0] ch_stat_1;	//reg [1:0] ch_stat_1;    wire [1:0] ch_stat_2;	//reg [1:0] ch_stat_2;	 wire [1:0] req_clr_1;	 wire [1:0] req_clr_2;	 wire [2:0] floor_1;	 wire [2:0] floor_2;	 wire des_clr_1;	 wire des_clr_2;	 //e_one///	 wire stop;			//close manhand//	 wire [1:0] drive;		  //drive驅(qū)動//	 wire inc_1;//	 wire inc_2;	 wire request_1 ;	 wire request_2 ;	 wire call_1;			/////////////////	 wire call_2;	 wire r_up_1;	 wire r_up_2;					  //上有請求	 wire r_down_1;	 wire r_down_2;	 wire move1;					  //eone 內(nèi)部信號，電梯開始從n層到第n+1層	 wire move2;						//  應該做為輸出。。		  ///////////////////////////////	 wire pv_in1,pv_out1,le1;	 wire pv_in2,pv_out2,le2;	 	 wire load_enable_low,load_enable_high,load_enable1,load_enable2;	 	 encoder4 LE_encoder(.m0_out(load_enable_low),.m1_out(load_enable_high),	                     .m2_out(load_enable1),.m3_out(load_enable2),	                     .code(code),.encoder4_in(load_enable));	 cu_two g_cu(.stat_1(run_state_1), .stat_2(run_state_2), .mov_1(mov_1), .mov_2(mov_2), .ch_stat_1(ch_stat_1),	             .ch_stat_2(ch_stat_2), .req_clr_1(req_clr_1), .req_clr_2(req_clr_2), .des_1(des_clr_1), 					 .des_2(des_clr_2),  .req_1(req_out_1), .req_2(req_out_2), .up_1(up_1), .up_2(up_2),.down_1(down_1),					  .down_2(down_2),.now_1(now_1),					  .now_2(now_2), .stop_1(stop_1), .stop_2(stop_2), .sel_1(call_1), .sel_2(call_2),					  .floor_1(floor_1), .floor_2(floor_2));//ok     e_one g_1(.clk(clk), .reset(reset), .re_in(re_in), .open(open_1), .close(close_1), .stop(stop_1), .load_enable(load_enable1),	           .register_in_0(des_req[0]),.register_in_1(des_req[1]),.register_in_2(des_req[2]), .register_in_3(des_req[3]),				  .register_in_4(des_req[4]),.register_in_5(des_req[5]),.register_in_6(des_req[6]),.register_in_7(des_req[7]),	           .drive(mov_1),.clear(des_clr_1), .req_up(r_up_1), .req_down(r_down_1), .d_ffloor(d_floor_1),				  .floor(floor_1),.lamp(run_state_1), .request(request_1), .call(call_1),				  .move(move1),.up(up_1),.down(down_1), .now(now_1) ,.pv_in(pv_out2), .pv_out(pv_in1),.le(le1));		 //ok    e_one g_2(.clk(~clk), .reset(reset), .re_in(re_in), .open(open_2),.close(close_2),.stop(stop_2), .load_enable(load_enable2),	           .register_in_0(des_req[0]),.register_in_1(des_req[1]),.register_in_2(des_req[2]), .register_in_3(des_req[3]),				  .register_in_4(des_req[4]),.register_in_5(des_req[5]),.register_in_6(des_req[6]),.register_in_7(des_req[7]),	           .drive(mov_2), .clear(des_clr_2), .req_up(r_up_2), .req_down(r_down_2), .d_ffloor(d_floor_2),				  .floor(floor_2), .lamp(run_state_2), .request(request_2), .call(call_2),				  .move(move2),.up(up_2), .down(down_2), .now(now_2), .pv_in(pv_out1), .pv_out(pv_in2),.le(le2));	 request re(.clk(clk), .reset(reset), .drive_1(request_1), .drive_2(request_2), .load_enable_low(load_enable_low),.load_enable_high(load_enable_high),	            .floor_1(floor_1),.floor_2(floor_2), 	            .req_clr_1(req_clr_1), .req_clr_2(req_clr_2), .req_in_0({1'b0,des_req[0]}), .req_in_1({des_req[3],des_req[2]}), .req_in_2({des_req[5],des_req[4]}), 					.req_in_3({des_req[7],des_req[6]}), .req_in_4({des_req[1],des_req[0]}), .req_in_5({des_req[3],des_req[2]}), .req_in_6({des_req[5],des_req[4]}), 					.req_in_7({des_req[7],1'b0}), .req_out_1(req_out_1), .req_out_2(req_out_2), .r_up_1(r_up_1),  ////					.r_up_2(r_up_2), .r_down_1(r_down_1), .r_down_2(r_down_2));	 pv pv_one(.pv_in(pv_in1), .pv_out(pv_out1),.clk(clk),.le(le1), .reset(reset));	 pv pv_two(.pv_in(pv_in2), .pv_out(pv_out2),.clk(~clk),.le(le2), .reset(reset));endmodule	  // 有請求時，request 信號，判斷本層上，下，本層是否有信號	  // 有請求時，request 信號，判斷本層是否為目的。	  // 	在e_one 中，與des 的信號相結(jié)合，輸出給 cu_two。