`timescale 1ns / 1ps////////////////////////////////////////////////////////////////////////////////// Company: // Engineer://// Create Date:    08:51:20 01/09/07// Design Name:    // Module Name:    l_cu// Project Name:   // Target Device:  // Tool versions:  // Description://// Dependencies:// // Revision:// Revision 0.01 - File Created// Additional Comments:// ////////////////////////////////////////////////////////////////////////////////module l_cu(clk_i,rst_i,re_in,open,close,floor,stop,oopen,cclose,clear,move,FLE,request,call,pv_in,pv_out,le);  input         clk_i;  input         rst_i;  input         re_in;    // 重新輸入數(shù)據(jù)  //input         set;	//set 為1時可以直接置數(shù)。  input         open;       //手動open信號  input         close;		//手動close信號	  input   [2:0] floor;       //電梯在哪一層。  input  stop;             //要不要停。。。   input pv_in;  output oopen;              //給電梯的open信號  output cclose;            //給電梯的close信號  output clear;              //電梯目的寄存器清零信號  output move;                //電梯繼續(xù)動使能信號//引出燈開顯示電梯在運行（上，下樓中）  output FLE;               //樓層變化使能信號  output request;					//請求調(diào)度信號  output call;  output pv_out,le;    reg oopen;  reg cclose;  reg clear;  reg move;  reg FLE;  reg request;  reg call;  reg pv_out,le;    reg [3:0] state;	  reg [3:0] temp; // wire sstop_out; // regis #(1) sstop(.register_in(stop),.register_out(sstop_out), .reset(rst_i), .clk(stop), .clr(FLE));  always @ (posedge clk_i or negedge rst_i)     begin	     if(!rst_i)		      begin				   state <= 4'b0000;						  //state = 111 時，idle					temp  <= 4'b0000;				end        else		    begin			 										case (state)				     4'b0000:  					     begin  						     if(re_in)								     begin								    temp <= state + 1;							       state <= 'b1111;								  end							  else							    if(pv_in)								   begin								    temp <= state+ 1;									 state <= 'b1111;									end								  else								  begin							       state <= 4'b0001; 									 								  end					     end					  4'b0001:					     begin						     if(re_in)							     begin								    temp <= state + 1;							       state <= 'b1111;								  end							  else						         state <= 4'b0010; end					  4'b0010:					     begin  						     if(re_in)							     begin								    temp <= state + 1;							       state <= 'b1111;								  end							  else									state <= 4'b0011;						  end					  4'b0011:					     begin 						     if(re_in)							     begin								    temp <= state + 1;							       state <= 'b1111;								  end							  else					          if(!stop)     						       begin					    			   state <= 4'b0000;                            end					   		 else								    if(close)							    	    state <= 4'b0101;																											   						   	    else								       state <= 4'b0100; 						  end					  4'b0100:					     begin 						     if(re_in)							     begin								    temp <= state + 1;							       state <= 'b1111;								  end							  else						   						      if(close)								    state <= 4'b0101;								else					     					             state <= 4'b0101; 						  end					  4'b0101:					     begin 						     if(re_in)							     begin								    temp <= state + 1;							       state <= 'b1111;								  end							  else							   begin 						   						      if(open)								    state <= 4'b0011;								else									 state <= 4'b0110; 								end						  end 					  4'b0110:					     begin						     if(re_in)							     begin								    temp <= state + 1;							       state <= 'b1111;								  end							  else						   						         state <= 4'b0111; end					  4'b1110:					     begin						     if(re_in)							     begin								    temp <= state + 1;							       state <= 'b1111;								  end							  else						   						         state <= 4'b0000; end					  4'b1111:					     begin 						     if(re_in)							      state <= 4'b1111; 							  else						     if(!pv_in)							  begin							      state <= temp;								end							  else 					 		      state <= 'b1111;		 					 	  end					  default:					    begin					 	     if(re_in )							     begin								    temp <= state + 1;							       state <= 'b1111;								  end							  else					   						         state <= state + 1; 					     						 end				   endcase 		  			 end	  end		  always @ (state or pv_in or rst_i)    begin	    FLE = 'b0;		 oopen = 'b0;		 cclose = 'b0;		 clear = 'b0;		 move = 'b0;		 request = 'b0;		 call = 'b0;		 pv_out = 0;		 le = 0;		 state = state;		 case (state)		    4'b0000:			     begin 				     if(!rst_i)					     FLE = 'b0;	 ///???????					  else   					  begin					     FLE = 'b1;					     					     					     if(pv_in) 					     pv_out = 0;					     else					     begin					     pv_out = 1;					     le = 1;					     end					  end				  end			 4'b0001:				        request = 'b1;				     			 4'b0010://			     if(sstop_out)	  //在該層停留才開門    				  call = 'b1;			     			 4'b0011:			 begin               if(stop)			         begin oopen = 'b1;  end               else					   begin oopen = 'b0;  end                  pv_out = 0;		        			le = 1;				end			  //   begin   end			 4'b0100:	  		       begin   		     	    if(open)	    			    begin oopen = 'b1;	end					 else 					    begin oopen = 'b0;	  end	   			 if (close)	   			    begin cclose = 'b1;	  end					 else					    begin cclose = 'b0;   end				 end			 4'b0101:			     begin  				      if(!open)						    cclose = 'b1;                  else 						    cclose = 'b0;					   if(open)						    oopen = 'b1;					   else 						    oopen = 'b0;		 		  			     end				 4'b0110:			     begin  move = 'b1; end  //請求調(diào)度信號			 			 4'b1111:			 begin			     if(temp == 4'b0001 && !pv_in)			        begin			            pv_out = 1;			            le = 1;			            end			     else			     pv_out = 0;			     end			 default:			     begin    				     FLE = 'b0;					  request = 'b0;					  call = 'b0;					  oopen = 'b0;					  cclose = 'b0;				  end        endcase			   endendmodule