`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    14:44:44 01/10/07
// Design Name:    
// Module Name:    lamp
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module lamp(lamp_out,reset, clk,drive);
   
  //  input [1:0] lamp_in;
    input reset;				//只要恢復(fù)初態(tài)即可
    input clk;
	 input [1:0] drive;       //lamp=0 時用到		注意信號到達(dá)的時刻。。。

	 output [1:0] lamp_out;

	 reg [1:0] lamp_out;			//output

	 reg [1:0] state;

	 always @ (posedge clk or negedge reset)
	    begin
		   if(!reset)
		     begin
			    state <= 2'b00;
			  end
			else
			  begin

			   	   case (drive)
 			   	   	2'b01: begin state <= 2'b01; end	
		   		    	2'b10: begin state <= 2'b10; end
			   			2'b00: begin state <= 2'b00; end
				      	default: begin state <= state;end
				 endcase  
			  end
		 end


 always @ (state)
    begin
	    lamp_out = state;
	 end

/*	  always @ (posedge clk or negedge reset)
	     begin
		    if(!reset)
			    lamp_out <= 2'b00;
			 else 
			    lamp_out <= state;
		  end
 */
endmodule