`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    00:31:49 01/15/07
// Design Name:    
// Module Name:    total_des
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module total_des(req_up, req_down, des_up, des_down, up, down);

    input req_up;
    input req_down;
    input des_up;
    input des_down;
    output up;		 reg up;
    output down;	 reg down;

	always @(req_up or req_down or des_up or des_down)
	begin
		if (req_up || des_up)
			up = 1;
		else up = 0;
		if (req_down || des_down)
			down = 1;
		else down = 0;

	end

endmodule