module encoder4(m0_out,m1_out,m2_out,m3_out,code,encoder4_in);    input encoder4_in;    input [1:0] code;    output m0_out,m1_out,m2_out,m3_out;        reg m0_out,m1_out,m2_out,m3_out;        always@(encoder4_in or code)    begin        m0_out = 0;        m1_out = 0;        m2_out = 0;        m3_out = 0;                case(code)            2'b00: begin m0_out = encoder4_in; end            2'b01: begin m1_out = encoder4_in; end            2'b10: begin m2_out = encoder4_in; end            2'b11: begin m3_out = encoder4_in; end        endcase    endendmodule