`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   11:02:20 01/26/2007
// Design Name:   tt
// Module Name:   tttest.v
// Project Name:  lift
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: tt
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module tttest_v;

	// Inputs
	reg load_enable;
	reg register_in_0;
	reg register_in_1;
	reg register_in_2;
	reg register_in_3;
	reg register_in_4;
	reg register_in_5;
	reg register_in_6;
	reg register_in_7;
	reg reset;
	reg request;
	reg [2:0] floor;
	reg des_clr;
	reg clk;

	// Outputs
	wire [7:0] register_out;
	wire up;
	wire down;
	wire now;

	// Instantiate the Unit Under Test (UUT)
	tt uut (
		.load_enable(load_enable), 
		.register_in_0(register_in_0), 
		.register_in_1(register_in_1), 
		.register_in_2(register_in_2), 
		.register_in_3(register_in_3), 
		.register_in_4(register_in_4), 
		.register_in_5(register_in_5), 
		.register_in_6(register_in_6), 
		.register_in_7(register_in_7), 
		.register_out(register_out), 
		.reset(reset), 
		.request(request), 
		.floor(floor), 
		.des_clr(des_clr), 
		.clk(clk), 
		.up(up), 
		.down(down), 
		.now(now)
	);

	initial begin
		// Initialize Inputs
		load_enable = 0;
		register_in_0 = 0;
		register_in_1 = 0;
		register_in_2 = 0;
		register_in_3 = 0;
		register_in_4 = 0;
		register_in_5 = 0;
		register_in_6 = 0;
		register_in_7 = 0;
		reset = 0;
		request = 0;
		floor = 0;
		des_clr = 0;
		clk = 0;

		// Wait 100 ns for global reset to finish
		#100;
		reset = 1;
		# 150;
		load_enable = 1;
		# 50;
		register_in_0 = 1;
		register_in_1 = 0;
		register_in_2 = 1;
		register_in_3 = 1;
		register_in_4 = 0;
		register_in_5 = 1;
		register_in_6 = 1;
		register_in_7 = 0;

		# 100;
		load_enable = 0;
		# 100 request = 1;
		#350;
		des_clr = 1;
		# 100 floor = 1;
		# 250 floor = 2;
		# 250 floor = 3;
		# 250 floor = 4;
		# 250 floor = 5;
		# 250 floor = 6;
		# 250 floor = 7;

		# 200 des_clr = 0;

		#1000 $stop;

        
		// Add stimulus here

	end

	always #100 clk = ~clk;
      
endmodule