`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   10:35:56 01/26/2007
// Design Name:   lamp
// Module Name:   lamptest.v
// Project Name:  lift
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: lamp
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module lamptest_v;

	// Inputs
	reg reset;
	reg clk;
	reg [1:0] drive;

	// Outputs
	wire [1:0] lamp_out;

	// Instantiate the Unit Under Test (UUT)
	lamp uut (
		.lamp_out(lamp_out), 
		.reset(reset), 
		.clk(clk), 
		.drive(drive)
	);

	initial begin
		// Initialize Inputs
		reset = 1;
		clk = 0;
		drive = 0;

		// Wait 100 ns for global reset to finish
		#200 reset = 0;

		# 350 reset = 1;

		#100;
      reset = 1;
		drive = 'b01;
		
		# 350;
		drive = 'b10;
		# 400;
		drive = 'b00; 
		// Add stimulus here

		# 1000 $stop;

	end

	always #100 clk = ~clk;
      
endmodule