---------------------------------------------------------------------------------- Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.----------------------------------------------------------------------------------   ____  ____--  /   /\/   /-- /___/  \  /    Vendor: Xilinx-- \   \   \/     Version: H.38--  \   \         Application: netgen--  /   /         Filename: g_ele_translate.vhd-- /___/   /\     Timestamp: Fri Jan 26 12:04:37 2007-- \   \  /  \ --  \___\/\___\--             -- Command: -intstyle ise -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim g_ele.ngd g_ele_translate.vhd -- Device: v100pq240-4-- Design Name: g_ele--             -- Purpose:    --     This VHDL netlist is a verification model and uses simulation --     primitives which may not represent the true implementation of the --     device, however the netlist is functionally correct and should not --     be modified. This file cannot be synthesized and should only be used --     with supported simulation tools.--             -- Reference:  --     Development System Reference Guide, Chapter 23--     Synthesis and Verification Design Guide, Chapter 6--             --------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;library SIMPRIM;use SIMPRIM.VCOMPONENTS.ALL;use SIMPRIM.VPACKAGE.ALL;entity g_ele is  port (    close_1 : in STD_LOGIC := 'X';     close_2 : in STD_LOGIC := 'X';     clk : in STD_LOGIC := 'X';     load_enable : in STD_LOGIC := 'X';     reset : in STD_LOGIC := 'X';     open_1 : in STD_LOGIC := 'X';     open_2 : in STD_LOGIC := 'X';     re_in : in STD_LOGIC := 'X';     des_req : in STD_LOGIC_VECTOR ( 7 downto 0 );     code : in STD_LOGIC_VECTOR ( 1 downto 0 );     floor_1 : out STD_LOGIC_VECTOR ( 2 downto 0 );     floor_2 : out STD_LOGIC_VECTOR ( 2 downto 0 );     d_floor_1 : out STD_LOGIC_VECTOR ( 7 downto 0 );     d_floor_2 : out STD_LOGIC_VECTOR ( 7 downto 0 );     run_state_1 : out STD_LOGIC_VECTOR ( 1 downto 0 );     run_state_2 : out STD_LOGIC_VECTOR ( 1 downto 0 )   );end g_ele;architecture Structure of g_ele is  type STD_LOGIC_VECTOR1 is array (natural range <>) of STD_LOGIC;  type STD_LOGIC_VECTOR2 is array (natural range <>, natural range <>) of STD_LOGIC;  type STD_LOGIC_VECTOR3 is array (natural range <>, natural range <>, natural range <>) of STD_LOGIC;  type STD_LOGIC_VECTOR4 is array (natural range <>, natural range <>, natural range <>, natural range <>) of STD_LOGIC;  signal close_1_IBUF : STD_LOGIC;   signal close_2_IBUF : STD_LOGIC;   signal clk_BUFGP : STD_LOGIC;   signal load_enable_IBUF : STD_LOGIC;   signal reset_IBUF : STD_LOGIC;   signal open_1_IBUF : STD_LOGIC;   signal open_2_IBUF : STD_LOGIC;   signal re_in_IBUF : STD_LOGIC;   signal down_1 : STD_LOGIC;   signal down_2 : STD_LOGIC;   signal pv_in1 : STD_LOGIC;   signal pv_in2 : STD_LOGIC;   signal re_r_down_1 : STD_LOGIC;   signal re_r_down_2 : STD_LOGIC;   signal call_1 : STD_LOGIC;   signal call_2 : STD_LOGIC;   signal up_1 : STD_LOGIC;   signal up_2 : STD_LOGIC;   signal g_cu_stop_1 : STD_LOGIC;   signal g_cu_stop_2 : STD_LOGIC;   signal des_req_1_IBUF : STD_LOGIC;   signal code_1_IBUF : STD_LOGIC;   signal des_req_4_IBUF : STD_LOGIC;   signal des_req_0_IBUF : STD_LOGIC;   signal des_req_2_IBUF : STD_LOGIC;   signal N1766 : STD_LOGIC;   signal code_0_IBUF : STD_LOGIC;   signal des_req_7_IBUF : STD_LOGIC;   signal des_req_6_IBUF : STD_LOGIC;   signal Q_n0009 : STD_LOGIC;   signal load_enable_low : STD_LOGIC;   signal des_req_5_IBUF : STD_LOGIC;   signal le2 : STD_LOGIC;   signal des_req_3_IBUF : STD_LOGIC;   signal load_enable_high : STD_LOGIC;   signal pv_one_pv_out : STD_LOGIC;   signal pv_two_pv_out : STD_LOGIC;   signal request_1 : STD_LOGIC;   signal request_2 : STD_LOGIC;   signal re_r_up_1 : STD_LOGIC;   signal re_r_up_2 : STD_LOGIC;   signal load_enable1 : STD_LOGIC;   signal load_enable2 : STD_LOGIC;   signal g_cu_des_1 : STD_LOGIC;   signal g_cu_des_2 : STD_LOGIC;   signal le1 : STD_LOGIC;   signal g_2_des_one_now : STD_LOGIC;   signal g_1_des_one_now : STD_LOGIC;   signal g_2_FLE : STD_LOGIC;   signal g_2_des_one_down : STD_LOGIC;   signal g_2_des_one_up : STD_LOGIC;   signal g_1_FLE : STD_LOGIC;   signal g_1_des_one_down : STD_LOGIC;   signal N1 : STD_LOGIC;   signal g_1_des_one_up : STD_LOGIC;   signal pv_two_pv_out_N0 : STD_LOGIC;   signal g_1_FR_one_N2 : STD_LOGIC;   signal g_2_FR_one_N2 : STD_LOGIC;   signal g_1_des_one_MUX_BLOCK_N1 : STD_LOGIC;   signal N1452 : STD_LOGIC;   signal N1454 : STD_LOGIC;   signal N1456 : STD_LOGIC;   signal N1458 : STD_LOGIC;   signal N1460 : STD_LOGIC;   signal N1462 : STD_LOGIC;   signal g_1_des_one_N31 : STD_LOGIC;   signal N1565 : STD_LOGIC;   signal g_1_des_one_MUX_BLOCK_floor_1_MUXF51 : STD_LOGIC;   signal g_1_des_one_MUX_BLOCK_floor_1_MUXF53 : STD_LOGIC;   signal g_1_des_one_MUX_BLOCK_N5 : STD_LOGIC;   signal N1571 : STD_LOGIC;   signal N1696 : STD_LOGIC;   signal g_1_des_one_MUX_BLOCK_N6 : STD_LOGIC;   signal g_1_des_one_n0001 : STD_LOGIC;   signal g_1_des_one_n0003 : STD_LOGIC;   signal g_1_des_one_n0005 : STD_LOGIC;   signal g_1_des_one_n0011 : STD_LOGIC;   signal g_1_des_one_n0007 : STD_LOGIC;   signal g_1_des_one_n0013 : STD_LOGIC;   signal g_1_des_one_n0009 : STD_LOGIC;   signal g_1_des_one_MUX_BLOCK_N8 : STD_LOGIC;   signal g_1_des_one_n0015 : STD_LOGIC;   signal N1717 : STD_LOGIC;   signal g_1_des_one_n0016 : STD_LOGIC;   signal g_1_des_one_n0017 : STD_LOGIC;   signal N1588 : STD_LOGIC;   signal N1427 : STD_LOGIC;   signal N1705 : STD_LOGIC;   signal g_1_des_one_MUX_BLOCK_N11 : STD_LOGIC;   signal g_1_des_one_MUX_BLOCK_N3 : STD_LOGIC;   signal g_1_des_one_MUX_BLOCK_N4 : STD_LOGIC;   signal g_1_des_one_n0094 : STD_LOGIC;   signal g_1_des_one_n0098 : STD_LOGIC;   signal N1598 : STD_LOGIC;   signal N1682 : STD_LOGIC;   signal g_1_des_one_n0096 : STD_LOGIC;   signal g_1_des_one_MUX_BLOCK_N7 : STD_LOGIC;   signal N1583 : STD_LOGIC;   signal g_1_des_one_MUX_BLOCK_floor_1_MUXF52 : STD_LOGIC;   signal g_1_des_one_MUX_BLOCK_n0018 : STD_LOGIC;   signal g_1_des_one_n0092 : STD_LOGIC;   signal g_1_des_one_n0100 : STD_LOGIC;   signal g_1_des_one_MUX_BLOCK_floor_1_MUXF5 : STD_LOGIC;   signal g_1_des_one_n0102 : STD_LOGIC;   signal N1664 : STD_LOGIC;   signal g_1_des_one_n0104 : STD_LOGIC;   signal N1700 : STD_LOGIC;   signal g_1_des_one_MUX_BLOCK_N10 : STD_LOGIC;   signal g_1_des_one_MUX_BLOCK_N9 : STD_LOGIC;   signal N1563 : STD_LOGIC;   signal g_1_des_one_n0106 : STD_LOGIC;   signal N1715 : STD_LOGIC;   signal g_1_des_one_MUX_BLOCK_floor_1_MUXF54 : STD_LOGIC;   signal g_1_des_one_MUX_BLOCK_N2 : STD_LOGIC;   signal g_1_des_one_MUX_BLOCK_floor_1_MUXF55 : STD_LOGIC;   signal g_1_des_one_MUX_BLOCK_N12 : STD_LOGIC;   signal g_2_des_one_MUX_BLOCK_N1 : STD_LOGIC;   signal N1510 : STD_LOGIC;   signal N1438 : STD_LOGIC;   signal N1546 : STD_LOGIC;   signal N1550 : STD_LOGIC;   signal N1450 : STD_LOGIC;   signal g_2_des_one_N31 : STD_LOGIC;   signal N1562 : STD_LOGIC;   signal g_2_des_one_MUX_BLOCK_floor_1_MUXF51 : STD_LOGIC;   signal g_2_des_one_MUX_BLOCK_floor_1_MUXF53 : STD_LOGIC;   signal g_2_des_one_MUX_BLOCK_N5 : STD_LOGIC;   signal N1568 : STD_LOGIC;   signal N1698 : STD_LOGIC;   signal g_2_des_one_MUX_BLOCK_N6 : STD_LOGIC;   signal g_2_des_one_n0001 : STD_LOGIC;   signal g_2_des_one_n0003 : STD_LOGIC;   signal g_2_des_one_n0005 : STD_LOGIC;   signal g_2_des_one_n0011 : STD_LOGIC;   signal g_2_des_one_n0007 : STD_LOGIC;   signal g_2_des_one_n0013 : STD_LOGIC;   signal g_2_des_one_n0009 : STD_LOGIC;   signal g_2_des_one_MUX_BLOCK_N8 : STD_LOGIC;   signal g_2_des_one_n0015 : STD_LOGIC;   signal CHOICE1561 : STD_LOGIC;   signal g_2_des_one_n0016 : STD_LOGIC;   signal g_2_des_one_n0017 : STD_LOGIC;   signal N1585 : STD_LOGIC;   signal N1426 : STD_LOGIC;   signal N1551 : STD_LOGIC;   signal g_2_des_one_MUX_BLOCK_N11 : STD_LOGIC;   signal g_2_des_one_MUX_BLOCK_N3 : STD_LOGIC;   signal g_2_des_one_MUX_BLOCK_N4 : STD_LOGIC;   signal g_2_des_one_n0094 : STD_LOGIC;   signal g_2_des_one_n0098 : STD_LOGIC;   signal N1530 : STD_LOGIC;   signal N1684 : STD_LOGIC;   signal g_2_des_one_n0096 : STD_LOGIC;   signal g_2_des_one_MUX_BLOCK_N7 : STD_LOGIC;   signal N1518 : STD_LOGIC;   signal g_2_des_one_MUX_BLOCK_floor_1_MUXF52 : STD_LOGIC;   signal g_2_des_one_MUX_BLOCK_n0018 : STD_LOGIC;   signal g_2_des_one_n0092 : STD_LOGIC;   signal g_2_des_one_n0100 : STD_LOGIC;   signal g_2_des_one_MUX_BLOCK_floor_1_MUXF5 : STD_LOGIC;   signal g_2_des_one_n0102 : STD_LOGIC;   signal N1666 : STD_LOGIC;   signal g_2_des_one_n0104 : STD_LOGIC;   signal N1702 : STD_LOGIC;   signal g_2_des_one_MUX_BLOCK_N10 : STD_LOGIC;   signal g_2_des_one_MUX_BLOCK_N9 : STD_LOGIC;   signal N1707 : STD_LOGIC;   signal g_2_des_one_n0106 : STD_LOGIC;   signal N1515 : STD_LOGIC;   signal g_2_des_one_MUX_BLOCK_floor_1_MUXF54 : STD_LOGIC;   signal g_2_des_one_MUX_BLOCK_N2 : STD_LOGIC;   signal g_2_des_one_MUX_BLOCK_floor_1_MUXF55 : STD_LOGIC;   signal g_2_des_one_MUX_BLOCK_N12 : STD_LOGIC;   signal N1424 : STD_LOGIC;   signal N1425 : STD_LOGIC;   signal g_2_cu_one_N30 : STD_LOGIC;   signal g_cu_N20 : STD_LOGIC;   signal g_2_cu_one_N23 : STD_LOGIC;   signal N1586 : STD_LOGIC;   signal N1632 : STD_LOGIC;   signal g_cu_n0048 : STD_LOGIC;   signal N1631 : STD_LOGIC;   signal g_cu_MUX_BLOCK_n0009 : STD_LOGIC;   signal g_2_cu_one_N4 : STD_LOGIC;   signal N1628 : STD_LOGIC;   signal N1542 : STD_LOGIC;   signal N1560 : STD_LOGIC;   signal g_cu_n0052 : STD_LOGIC;   signal N1539 : STD_LOGIC;   signal g_2_cu_one_N01 : STD_LOGIC;   signal g_cu_MUX_BLOCK_n0003 : STD_LOGIC;   signal re_MUX_BLOCK_n0032 : STD_LOGIC;   signal N1624 : STD_LOGIC;   signal re_MUX_BLOCK_N25 : STD_LOGIC;   signal re_MUX_BLOCK_N26 : STD_LOGIC;   signal re_MUX_BLOCK_floor_1_1_MUXF54 : STD_LOGIC;   signal re_MUX_BLOCK_floor_2_1_MUXF54 : STD_LOGIC;   signal re_register_5_1_Q : STD_LOGIC;   signal re_register_3_0_Q : STD_LOGIC;   signal re_N31 : STD_LOGIC;   signal N1533 : STD_LOGIC;   signal re_register_2_1_Q : STD_LOGIC;   signal re_register_0_0_Q : STD_LOGIC;   signal N1576 : STD_LOGIC;   signal re_MUX_BLOCK_N20 : STD_LOGIC;   signal re_MUX_BLOCK_N23 : STD_LOGIC;   signal re_MUX_BLOCK_N19 : STD_LOGIC;   signal re_MUX_BLOCK_N18 : STD_LOGIC;   signal re_MUX_BLOCK_N27 : STD_LOGIC;   signal re_MUX_BLOCK_N28 : STD_LOGIC;   signal N1612 : STD_LOGIC;   signal N1620 : STD_LOGIC;   signal re_N21 : STD_LOGIC;   signal re_N14 : STD_LOGIC;   signal re_register_1_0_Q : STD_LOGIC;   signal re_n0268 : STD_LOGIC;   signal re_N20 : STD_LOGIC;   signal re_MUX_BLOCK_floor_2_1_MUXF53 : STD_LOGIC;   signal re_n0274 : STD_LOGIC;   signal re_register_3_1_Q : STD_LOGIC;   signal re_N16 : STD_LOGIC;   signal re_MUX_BLOCK_N9 : STD_LOGIC;   signal re_n0280 : STD_LOGIC;   signal re_register_1_1_Q : STD_LOGIC;   signal re_n0096 : STD_LOGIC;   signal re_MUX_BLOCK_N10 : STD_LOGIC;   signal re_n0276 : STD_LOGIC;   signal N1536 : STD_LOGIC;   signal re_n0282 : STD_LOGIC;   signal re_MUX_BLOCK_N12 : STD_LOGIC;   signal re_MUX_BLOCK_N1 : STD_LOGIC;   signal re_N29 : STD_LOGIC;   signal re_n0278 : STD_LOGIC;   signal re_MUX_BLOCK_floor_1_1_MUXF53 : STD_LOGIC;   signal re_MUX_BLOCK_N14 : STD_LOGIC;   signal re_n0284 : STD_LOGIC;   signal re_n0298_4_Q : STD_LOGIC;   signal re_MUX_BLOCK_N2 : STD_LOGIC;   signal re_n0290 : STD_LOGIC;   signal re_n0088 : STD_LOGIC;   signal re_MUX_BLOCK_N6 : STD_LOGIC;   signal re_MUX_BLOCK_N30 : STD_LOGIC;   signal N1579 : STD_LOGIC;   signal re_n0286 : STD_LOGIC;   signal re_MUX_BLOCK_floor_1_1_MUXF5 : STD_LOGIC;   signal re_n0092 : STD_LOGIC;   signal re_n0292 : STD_LOGIC;   signal re_n0298_5_Q : STD_LOGIC;   signal re_MUX_BLOCK_N29 : STD_LOGIC;   signal re_MUX_BLOCK_floor_1_1_MUXF57 : STD_LOGIC;   signal re_n0296_2_Q : STD_LOGIC;   signal re_n0288 : STD_LOGIC;   signal re_MUX_BLOCK_floor_2_1_MUXF56 : STD_LOGIC;   signal re_n0298_6_Q : STD_LOGIC;   signal re_MUX_BLOCK_N21 : STD_LOGIC;   signal re_MUX_BLOCK_floor_1_1_MUXF52 : STD_LOGIC;   signal re_MUX_BLOCK_N17 : STD_LOGIC;   signal re_MUX_BLOCK_floor_1_1_MUXF56 : STD_LOGIC;   signal re_n0296_3_Q : STD_LOGIC;   signal N1582 : STD_LOGIC;   signal re_n0080 : STD_LOGIC;   signal re_register_6_0_Q : STD_LOGIC;   signal re_MUX_BLOCK_floor_2_1_MUXF55 : STD_LOGIC;   signal re_register_6_1_Q : STD_LOGIC;   signal re_MUX_BLOCK_N4 : STD_LOGIC;   signal re_register_7_1_Q : STD_LOGIC;   signal re_MUX_BLOCK_N16 : STD_LOGIC;   signal re_MUX_BLOCK_floor_2_1_MUXF51 : STD_LOGIC;   signal re_MUX_BLOCK_N13 : STD_LOGIC;   signal re_MUX_BLOCK_N11 : STD_LOGIC;   signal re_n0003 : STD_LOGIC;   signal re_n0005 : STD_LOGIC;   signal re_n0011 : STD_LOGIC;   signal re_n0007 : STD_LOGIC;   signal re_n0013 : STD_LOGIC;   signal re_n0009 : STD_LOGIC;   signal re_n0015 : STD_LOGIC;   signal re_n0021 : STD_LOGIC;   signal re_n0017 : STD_LOGIC;   signal re_n0023 : STD_LOGIC;   signal re_n0019 : STD_LOGIC;   signal re_n0025 : STD_LOGIC;   signal re_n0296_1_Q : STD_LOGIC;   signal re_n0027 : STD_LOGIC;   signal re_n0033 : STD_LOGIC;   signal re_n0029 : STD_LOGIC;   signal re_register_5_0_Q : STD_LOGIC;   signal re_n0272 : STD_LOGIC;   signal re_n0036 : STD_LOGIC;   signal re_N22 : STD_LOGIC;   signal re_MUX_BLOCK_N32 : STD_LOGIC;   signal re_MUX_BLOCK_N8 : STD_LOGIC;   signal re_n0296_5_Q : STD_LOGIC;   signal re_n0266 : STD_LOGIC;   signal re_register_4_1_Q : STD_LOGIC;   signal re_register_2_0_Q : STD_LOGIC;   signal re_MUX_BLOCK_floor_1_1_MUXF55 : STD_LOGIC;   signal re_MUX_BLOCK_N3 : STD_LOGIC;   signal N1618 : STD_LOGIC;   signal re_MUX_BLOCK_floor_1_1_MUXF51 : STD_LOGIC;   signal re_N28 : STD_LOGIC;   signal re_MUX_BLOCK_N15 : STD_LOGIC;   signal re_register_4_0_Q : STD_LOGIC;   signal re_n0270 : STD_LOGIC;   signal re_N19 : STD_LOGIC;   signal re_N23 : STD_LOGIC;   signal re_N30 : STD_LOGIC;   signal re_MUX_BLOCK_floor_2_1_MUXF52 : STD_LOGIC;   signal re_MUX_BLOCK_floor_2_1_MUXF5 : STD_LOGIC;   signal re_MUX_BLOCK_N22 : STD_LOGIC;   signal N1524 : STD_LOGIC;   signal re_MUX_BLOCK_N7 : STD_LOGIC;   signal re_n0298_2_Q : STD_LOGIC;   signal re_MUX_BLOCK_N24 : STD_LOGIC;   signal re_n0076 : STD_LOGIC;   signal N1573 : STD_LOGIC;   signal N1527 : STD_LOGIC;   signal re_MUX_BLOCK_N31 : STD_LOGIC;   signal re_MUX_BLOCK_n0035 : STD_LOGIC;   signal re_MUX_BLOCK_N5 : STD_LOGIC;   signal re_MUX_BLOCK_floor_2_1_MUXF57 : STD_LOGIC;   signal N1577 : STD_LOGIC;   signal g_1_cu_one_N17 : STD_LOGIC;   signal g_1_cu_one_N23 : STD_LOGIC;   signal N1629 : STD_LOGIC;   signal g_1_cu_one_N30 : STD_LOGIC;   signal g_1_cu_one_N01 : STD_LOGIC;   signal g_1_cu_one_N4 : STD_LOGIC;   signal N1580 : STD_LOGIC;   signal g_2_cu_one_N17 : STD_LOGIC;   signal N1688 : STD_LOGIC;   signal N1686 : STD_LOGIC;   signal N8 : STD_LOGIC;   signal N10 : STD_LOGIC;   signal CHOICE1808 : STD_LOGIC;   signal CHOICE1450 : STD_LOGIC;   signal CHOICE1413 : STD_LOGIC;   signal N1557 : STD_LOGIC;   signal N1556 : STD_LOGIC;   signal N1592 : STD_LOGIC;   signal CHOICE1406 : STD_LOGIC;   signal CHOICE1399 : STD_LOGIC;   signal CHOICE1365 : STD_LOGIC;   signal CHOICE1322 : STD_LOGIC;   signal N1512 : STD_LOGIC;   signal N1678 : STD_LOGIC;   signal CHOICE1298 : STD_LOGIC;   signal CHOICE1319 : STD_LOGIC;   signal N1589 : STD_LOGIC;   signal N1522 : STD_LOGIC;   signal N552 : STD_LOGIC;   signal CHOICE1409 : STD_LOGIC;   signal CHOICE1458 : STD_LOGIC;   signal N544 : STD_LOGIC;   signal N550 : STD_LOGIC;   signal N1674 : STD_LOGIC;   signal N1692 : STD_LOGIC;   signal N546 : STD_LOGIC;   signal N1559 : STD_LOGIC;   signal CHOICE1420 : STD_LOGIC;   signal CHOICE1477 : STD_LOGIC;   signal N1690 : STD_LOGIC;   signal N1694 : STD_LOGIC;   signal CHOICE1767 : STD_LOGIC;   signal CHOICE1340 : STD_LOGIC;   signal CHOICE1423 : STD_LOGIC;   signal N1521 : STD_LOGIC;   signal CHOICE1432 : STD_LOGIC;   signal N1610 : STD_LOGIC;   signal CHOICE1451 : STD_LOGIC;   signal N1676 : STD_LOGIC;   signal CHOICE1310 : STD_LOGIC;   signal N1658 : STD_LOGIC;   signal CHOICE1392 : STD_LOGIC;   signal CHOICE1431 : STD_LOGIC;   signal CHOICE1348 : STD_LOGIC;   signal CHOICE1499 : STD_LOGIC;   signal CHOICE1471 : STD_LOGIC;   signal CHOICE1315 : STD_LOGIC;   signal CHOICE1459 : STD_LOGIC;   signal CHOICE1439 : STD_LOGIC;   signal CHOICE1503 : STD_LOGIC;