);  g_2_cu_one_Ker231 : X_LUT2    generic map(      INIT => X"7"    )    port map (      ADR0 => g_2_cu_one_state(1),      ADR1 => g_2_cu_one_state(2),      O => g_2_cu_one_N23    );  g_2_FR_one_state_2 : X_FF    generic map(      INIT => '0'    )    port map (      I => g_2_FR_one_n0000(2),      CE => g_2_FLE,      RST => g_2_FR_one_state_2_GSR_OR,      CLK => Q_n0009,      O => g_2_FR_one_state(2),      SET => GND    );  g_2_lamp_one_state_0 : X_FF    generic map(      INIT => '0'    )    port map (      I => g_2_lamp_one_n0000(0),      RST => g_2_lamp_one_state_0_GSR_OR,      CLK => Q_n0009,      O => g_2_lamp_one_state(0),      CE => VCC,      SET => GND    );  g_2_des_one_floor_0_10 : X_LUT4    generic map(      INIT => X"2223"    )    port map (      ADR0 => g_2_FR_one_state(0),      ADR1 => g_2_des_one_N31,      ADR2 => g_2_des_one_register_out(3),      ADR3 => g_2_des_one_register_out(2),      O => g_2_des_one_MUX_BLOCK_N11    );  g_2_total_one_n00001 : X_LUT2    generic map(      INIT => X"E"    )    port map (      ADR0 => g_2_des_one_up,      ADR1 => re_r_up_2,      O => up_2    );  g_1_cu_one_Ker231 : X_LUT2    generic map(      INIT => X"7"    )    port map (      ADR0 => g_1_cu_one_state(1),      ADR1 => g_1_cu_one_state(2),      O => g_1_cu_one_N23    );  g_1_FR_one_state_2 : X_FF    generic map(      INIT => '0'    )    port map (      I => g_1_FR_one_n0000(2),      CE => g_1_FLE,      RST => g_1_FR_one_state_2_GSR_OR,      CLK => clk_BUFGP,      O => g_1_FR_one_state(2),      SET => GND    );  g_2_lamp_one_state_1 : X_FF    generic map(      INIT => '0'    )    port map (      I => g_2_lamp_one_n0000(1),      RST => g_2_lamp_one_state_1_GSR_OR,      CLK => Q_n0009,      O => g_2_lamp_one_state(1),      CE => VCC,      SET => GND    );  g_2_des_one_n00071 : X_LUT4    generic map(      INIT => X"8000"    )    port map (      ADR0 => code_0_IBUF,      ADR1 => code_1_IBUF,      ADR2 => load_enable_IBUF,      ADR3 => des_req_4_IBUF,      O => g_2_des_one_n0007    );  g_1_total_one_n00001 : X_LUT2    generic map(      INIT => X"E"    )    port map (      ADR0 => g_1_des_one_up,      ADR1 => re_r_up_1,      O => up_1    );  pv_two_pv_out_0 : X_FF    generic map(      INIT => '0'    )    port map (      I => pv_in2,      CE => le2,      RST => pv_two_pv_out_GSR_OR,      CLK => Q_n0009,      O => pv_two_pv_out,      SET => GND    );  pv_one_pv_out_1 : X_FF    generic map(      INIT => '0'    )    port map (      I => pv_in1,      CE => le1,      RST => pv_one_pv_out_GSR_OR,      CLK => clk_BUFGP,      O => pv_one_pv_out,      SET => GND    );  XST_VCC : X_ONE    port map (      O => N1    );  g_1_lamp_one_state_0 : X_FF    generic map(      INIT => '0'    )    port map (      I => g_1_lamp_one_n0000(0),      RST => g_1_lamp_one_state_0_GSR_OR,      CLK => clk_BUFGP,      O => g_1_lamp_one_state(0),      CE => VCC,      SET => GND    );  g_1_lamp_one_state_1 : X_FF    generic map(      INIT => '0'    )    port map (      I => g_1_lamp_one_n0000(1),      RST => g_1_lamp_one_state_1_GSR_OR,      CLK => clk_BUFGP,      O => g_1_lamp_one_state(1),      CE => VCC,      SET => GND    );  g_1_lamp_one_n0000_1_1 : X_LUT3    generic map(      INIT => X"C4"    )    port map (      ADR0 => g_cu_mov_1(0),      ADR1 => g_cu_mov_1(1),      ADR2 => g_1_lamp_one_state(1),      O => g_1_lamp_one_n0000(1)    );  pv_two_pv_out_N01_INV_0 : X_INV    port map (      I => reset_IBUF,      O => pv_two_pv_out_N0    );  Q_n00091_INV_0 : X_INV    port map (      I => clk_BUFGP,      O => Q_n0009    );  LE_encoder_m0_out1 : X_LUT3    generic map(      INIT => X"10"    )    port map (      ADR0 => code_0_IBUF,      ADR1 => code_1_IBUF,      ADR2 => load_enable_IBUF,      O => load_enable_low    );  LE_encoder_m1_out1 : X_LUT3    generic map(      INIT => X"20"    )    port map (      ADR0 => code_0_IBUF,      ADR1 => code_1_IBUF,      ADR2 => load_enable_IBUF,      O => load_enable_high    );  LE_encoder_m3_out1 : X_LUT3    generic map(      INIT => X"80"    )    port map (      ADR0 => code_0_IBUF,      ADR1 => code_1_IBUF,      ADR2 => load_enable_IBUF,      O => load_enable2    );  g_1_FR_one_n0000_1_1 : X_LUT4    generic map(      INIT => X"C96C"    )    port map (      ADR0 => g_1_FR_one_state(0),      ADR1 => g_1_FR_one_state(1),      ADR2 => g_1_lamp_one_state(0),      ADR3 => g_1_lamp_one_state(1),      O => g_1_FR_one_n0000(1)    );  g_1_FR_one_state_1 : X_FF    generic map(      INIT => '0'    )    port map (      I => g_1_FR_one_n0000(1),      CE => g_1_FLE,      RST => g_1_FR_one_state_1_GSR_OR,      CLK => clk_BUFGP,      O => g_1_FR_one_state(1),      SET => GND    );  g_1_FR_one_state_0 : X_FF    generic map(      INIT => '0'    )    port map (      I => g_1_FR_one_n0000(0),      CE => g_1_FLE,      RST => g_1_FR_one_state_0_GSR_OR,      CLK => clk_BUFGP,      O => g_1_FR_one_state(0),      SET => GND    );  g_1_FR_one_n0000_0_1 : X_LUT3    generic map(      INIT => X"96"    )    port map (      ADR0 => g_1_FR_one_state(0),      ADR1 => g_1_lamp_one_state(0),      ADR2 => g_1_lamp_one_state(1),      O => g_1_FR_one_n0000(0)    );  d_floor_1_2_OBUF : X_BUF    port map (      I => g_1_des_one_register_out_2_1,      O => d_floor_1_2_OBUF_GTS_TRI    );  g_1_FR_one_n0000_2_2 : X_LUT2    generic map(      INIT => X"6"    )    port map (      ADR0 => g_1_FR_one_state(2),      ADR1 => g_1_FR_one_N2,      O => g_1_FR_one_n0000(2)    );  g_1_FR_one_n0000_2_1 : X_LUT4    generic map(      INIT => X"0180"    )    port map (      ADR0 => g_1_FR_one_state(0),      ADR1 => g_1_FR_one_state(1),      ADR2 => g_1_lamp_one_state(0),      ADR3 => g_1_lamp_one_state(1),      O => g_1_FR_one_N2    );  g_2_FR_one_n0000_1_1 : X_LUT4    generic map(      INIT => X"C96C"    )    port map (      ADR0 => g_2_FR_one_state(0),      ADR1 => g_2_FR_one_state(1),      ADR2 => g_2_lamp_one_state(0),      ADR3 => g_2_lamp_one_state(1),      O => g_2_FR_one_n0000(1)    );  g_2_FR_one_state_1 : X_FF    generic map(      INIT => '0'    )    port map (      I => g_2_FR_one_n0000(1),      CE => g_2_FLE,      RST => g_2_FR_one_state_1_GSR_OR,      CLK => Q_n0009,      O => g_2_FR_one_state(1),      SET => GND    );  g_2_FR_one_state_0 : X_FF    generic map(      INIT => '0'    )    port map (      I => g_2_FR_one_n0000(0),      CE => g_2_FLE,      RST => g_2_FR_one_state_0_GSR_OR,      CLK => Q_n0009,      O => g_2_FR_one_state(0),      SET => GND    );  g_2_FR_one_n0000_0_1 : X_LUT3    generic map(      INIT => X"96"    )    port map (      ADR0 => g_2_FR_one_state(0),      ADR1 => g_2_lamp_one_state(0),      ADR2 => g_2_lamp_one_state(1),      O => g_2_FR_one_n0000(0)    );  d_floor_1_7_OBUF : X_BUF    port map (      I => g_1_des_one_register_out_7_1,      O => d_floor_1_7_OBUF_GTS_TRI    );  g_2_FR_one_n0000_2_2 : X_LUT2    generic map(      INIT => X"6"    )    port map (      ADR0 => g_2_FR_one_state(2),      ADR1 => g_2_FR_one_N2,      O => g_2_FR_one_n0000(2)    );  g_2_FR_one_n0000_2_1 : X_LUT4    generic map(      INIT => X"0180"    )    port map (      ADR0 => g_2_FR_one_state(0),      ADR1 => g_2_FR_one_state(1),      ADR2 => g_2_lamp_one_state(0),      ADR3 => g_2_lamp_one_state(1),      O => g_2_FR_one_N2    );  g_1_des_one_n00071 : X_LUT4    generic map(      INIT => X"2000"    )    port map (      ADR0 => code_1_IBUF,      ADR1 => code_0_IBUF,      ADR2 => load_enable_IBUF,      ADR3 => des_req_4_IBUF,      O => g_1_des_one_n0007    );  g_cu_Mmux_n0008_n0008_0_Q : X_LUT4    generic map(      INIT => X"AF8F"    )    port map (      ADR0 => g_1_lamp_one_state(1),      ADR1 => g_1_lamp_one_state(0),      ADR2 => re_req_out_1(0),      ADR3 => N1462,      O => g_cu_MUX_BLOCK_n0008(0)    );  g_2_des_one_n00921111_G : X_LUT4    generic map(      INIT => X"EAAA"    )    port map (      ADR0 => load_enable2,      ADR1 => g_cu_des_2,      ADR2 => g_2_FR_one_state(0),      ADR3 => g_2_FR_one_state(2),      O => N1728    );  g_cu_Mmux_n0003_n0003_n0003 : X_LUT4    generic map(      INIT => X"AF8F"    )    port map (      ADR0 => g_2_lamp_one_state(1),      ADR1 => g_2_lamp_one_state(0),      ADR2 => re_req_out_2(0),      ADR3 => N1460,      O => g_cu_MUX_BLOCK_n0004(0)    );  re_n02704_SW1 : X_LUT4    generic map(      INIT => X"FF32"    )    port map (      ADR0 => re_register_1_0_Q,      ADR1 => load_enable_high,      ADR2 => re_register_1_1_Q,      ADR3 => load_enable_low,      O => N1519    );  g_cu_Mmux_n0003_n0003 : X_LUT4    generic map(      INIT => X"FA72"    )    port map (      ADR0 => g_2_lamp_one_state(1),      ADR1 => g_cu_n0083(2),      ADR2 => N1458,      ADR3 => g_2_lamp_one_state(0),      O => g_cu_MUX_BLOCK_n0003    );  g_cu_Mmux_n0003_n0003_SW0 : X_LUT4    generic map(      INIT => X"01AB"    )    port map (      ADR0 => g_2_lamp_one_state(0),      ADR1 => re_req_out_2(0),      ADR2 => re_req_out_2(1),      ADR3 => g_cu_n0083(1),      O => N1458    );  g_cu_Mmux_n0003_n0003_n0003_rn_0 : X_LUT4    generic map(      INIT => X"FD75"    )    port map (      ADR0 => re_req_out_2(1),      ADR1 => g_2_lamp_one_state(1),      ADR2 => N1456,      ADR3 => g_2_lamp_one_state(0),      O => g_cu_MUX_BLOCK_n0004(1)    );  g_cu_Mmux_n0008_n0008_0_SW0 : X_LUT4    generic map(      INIT => X"FFFE"    )    port map (      ADR0 => g_1_des_one_down,      ADR1 => re_r_down_1,      ADR2 => g_1_des_one_now,      ADR3 => re_req_out_1(1),