library verilog;use verilog.vl_types.all;entity sfifo is    port(        clk             : in     vl_logic;        wen             : in     vl_logic;        wptr            : in     vl_logic_vector(3 downto 0);        rptr            : in     vl_logic_vector(3 downto 0);        din             : in     vl_logic_vector(7 downto 0);        dout            : out    vl_logic_vector(7 downto 0)    );end sfifo;