--    File Name:  txmit.vhd--      Version:  1.1--         Date:  January 22, 2000--        Model:  Transmitter Chip----      Company:  Xilinx------   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY --                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY --                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR--                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.----                Copyright (c) 2000 Xilinx, Inc.--                All rights reservedlibrary ieee ;use ieee.std_logic_1164.all ;use ieee.std_logic_arith.all ;entity txmit isport (rst,clk16x,wrn : in std_logic ;	din : in std_logic_vector(7 downto 0) ;	tbre : out std_logic ;	tsre : out std_logic ;	sdo  : out std_logic ) ;end txmit ;architecture v1 of txmit issignal clk1x_enable : std_logic ;signal tsr : std_logic_vector (7 downto 0) ;signal tbr : std_logic_vector (7 downto 0) ;signal parity :  std_logic ;signal clkdiv :  unsigned (3 downto 0) ;signal clk1x :  std_logic ;signal no_bits_sent :  unsigned (3 downto 0) ;signal wrn1 :  std_logic ;signal wrn2 :  std_logic ;beginprocess (rst,clk16x)beginif rst = '1' thenwrn1 <= '1' ;wrn2 <= '1' ;elsif clk16x'event and clk16x = '1' thenwrn2 <= wrn1 ;wrn1 <= wrn ;end if ;end process ;process (rst,clk16x)beginif rst = '1' thenclk1x_enable <= '0' ;tbre <= '0' ;elsif clk16x'event and clk16x = '1' thenif wrn1 = '0' and wrn2 = '1' then tbre <= '0' ;clk1x_enable <= '1' ;elsif std_logic_vector(no_bits_sent) = "0010" thentbre <= '1' ;elsif std_logic_vector(no_bits_sent) = "1101" thenclk1x_enable <= '0' ;end if ;end if ;end process ;process (rst,wrn)beginif rst = '1' thentbr <= (others => '0') ;elsif wrn'event and wrn = '0' thentbr <= din ;end if ;end process ;process (rst,clk16x,clk1x_enable)beginif rst = '1' thenclkdiv <=  "0000" ;elsif clk16x'event and clk16x = '1' thenif clk1x_enable = '1' thenclkdiv <= clkdiv + "0001" ;end if ;end if ;end process ;clk1x <= clkdiv(3) ;process (rst,clk1x,no_bits_sent,tbr)beginif rst = '1' then sdo <= '1' ;tsre <= '1' ;tsr <= "00000000" ;parity <= '1' ;elsif clk1x'event and clk1x = '1' thenif std_logic_vector(no_bits_sent) = "0001" thentsr <= tbr ;tsre <= '0' ;elsif std_logic_vector(no_bits_sent) = "0010" thensdo <= '0' ;elsif std_logic_vector(no_bits_sent) >= "0011" and std_logic_vector(no_bits_sent) <= "1010" thentsr <= tsr(6 downto 0) & '0' ;sdo <= tsr(7) ;parity <= parity xor tsr(7) ;end if ;end if ;end process ;process (rst,clk1x,clk1x_enable)beginif rst = '1' or clk1x_enable = '0' thenno_bits_sent <= "0000" ;elsif clk1x'event and clk1x = '1' thenif clk1x_enable = '1' thenno_bits_sent <= no_bits_sent + "0001" ;end if ;end if ;end process ;end ;