{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "A8255.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/A8255.vhd" 35 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register portcout:I_portcout\|PortCOutRegQ\[3\] register portcout:I_portcout\|PortCOutRegQ\[3\] 267.17 MHz 3.743 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 267.17 MHz between source register \"portcout:I_portcout\|PortCOutRegQ\[3\]\" and destination register \"portcout:I_portcout\|PortCOutRegQ\[3\]\" (period= 3.743 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.577 ns + Longest register register " "Info: + Longest register to register delay is 3.577 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns portcout:I_portcout\|PortCOutRegQ\[3\] 1 REG LC_X34_Y16_N1 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y16_N1; Fanout = 7; REG Node = 'portcout:I_portcout\|PortCOutRegQ\[3\]'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "portcout.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/portcout.vhd" 388 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.101 ns) + CELL(0.075 ns) 1.176 ns portcout:I_portcout\|PortCOutRegD\[3\]~6934 2 COMB LC_X33_Y17_N5 1 " "Info: 2: + IC(1.101 ns) + CELL(0.075 ns) = 1.176 ns; Loc. = LC_X33_Y17_N5; Fanout = 1; COMB Node = 'portcout:I_portcout\|PortCOutRegD\[3\]~6934'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.176 ns" { portcout:I_portcout|PortCOutRegQ[3] portcout:I_portcout|PortCOutRegD[3]~6934 } "NODE_NAME" } } { "portcout.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/portcout.vhd" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.487 ns) + CELL(0.075 ns) 1.738 ns portcout:I_portcout\|PortCOutRegD\[3\]~6935 3 COMB LC_X34_Y17_N2 1 " "Info: 3: + IC(0.487 ns) + CELL(0.075 ns) = 1.738 ns; Loc. = LC_X34_Y17_N2; Fanout = 1; COMB Node = 'portcout:I_portcout\|PortCOutRegD\[3\]~6935'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.562 ns" { portcout:I_portcout|PortCOutRegD[3]~6934 portcout:I_portcout|PortCOutRegD[3]~6935 } "NODE_NAME" } } { "portcout.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/portcout.vhd" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.964 ns) + CELL(0.075 ns) 2.777 ns portcout:I_portcout\|PortCOutRegD\[3\]~6937 4 COMB LC_X33_Y16_N8 1 " "Info: 4: + IC(0.964 ns) + CELL(0.075 ns) = 2.777 ns; Loc. = LC_X33_Y16_N8; Fanout = 1; COMB Node = 'portcout:I_portcout\|PortCOutRegD\[3\]~6937'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.039 ns" { portcout:I_portcout|PortCOutRegD[3]~6935 portcout:I_portcout|PortCOutRegD[3]~6937 } "NODE_NAME" } } { "portcout.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/portcout.vhd" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.134 ns) + CELL(0.075 ns) 2.986 ns portcout:I_portcout\|PortCOutRegD\[3\]~6938 5 COMB LC_X33_Y16_N9 1 " "Info: 5: + IC(0.134 ns) + CELL(0.075 ns) = 2.986 ns; Loc. = LC_X33_Y16_N9; Fanout = 1; COMB Node = 'portcout:I_portcout\|PortCOutRegD\[3\]~6938'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.209 ns" { portcout:I_portcout|PortCOutRegD[3]~6937 portcout:I_portcout|PortCOutRegD[3]~6938 } "NODE_NAME" } } { "portcout.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/portcout.vhd" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.506 ns) + CELL(0.085 ns) 3.577 ns portcout:I_portcout\|PortCOutRegQ\[3\] 6 REG LC_X34_Y16_N1 7 " "Info: 6: + IC(0.506 ns) + CELL(0.085 ns) = 3.577 ns; Loc. = LC_X34_Y16_N1; Fanout = 7; REG Node = 'portcout:I_portcout\|PortCOutRegQ\[3\]'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.591 ns" { portcout:I_portcout|PortCOutRegD[3]~6938 portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "portcout.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/portcout.vhd" 388 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.385 ns ( 10.76 % ) " "Info: Total cell delay = 0.385 ns ( 10.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.192 ns ( 89.24 % ) " "Info: Total interconnect delay = 3.192 ns ( 89.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.577 ns" { portcout:I_portcout|PortCOutRegQ[3] portcout:I_portcout|PortCOutRegD[3]~6934 portcout:I_portcout|PortCOutRegD[3]~6935 portcout:I_portcout|PortCOutRegD[3]~6937 portcout:I_portcout|PortCOutRegD[3]~6938 portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "3.577 ns" { portcout:I_portcout|PortCOutRegQ[3] portcout:I_portcout|PortCOutRegD[3]~6934 portcout:I_portcout|PortCOutRegD[3]~6935 portcout:I_portcout|PortCOutRegD[3]~6937 portcout:I_portcout|PortCOutRegD[3]~6938 portcout:I_portcout|PortCOutRegQ[3] } { 0.000ns 1.101ns 0.487ns 0.964ns 0.134ns 0.506ns } { 0.000ns 0.075ns 0.075ns 0.075ns 0.075ns 0.085ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.023 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 3.023 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_M20 54 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 54; CLK Node = 'CLK'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "A8255.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/A8255.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.653 ns) + CELL(0.542 ns) 3.023 ns portcout:I_portcout\|PortCOutRegQ\[3\] 2 REG LC_X34_Y16_N1 7 " "Info: 2: + IC(1.653 ns) + CELL(0.542 ns) = 3.023 ns; Loc. = LC_X34_Y16_N1; Fanout = 7; REG Node = 'portcout:I_portcout\|PortCOutRegQ\[3\]'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.195 ns" { CLK portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "portcout.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/portcout.vhd" 388 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.32 % ) " "Info: Total cell delay = 1.370 ns ( 45.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.653 ns ( 54.68 % ) " "Info: Total interconnect delay = 1.653 ns ( 54.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.023 ns" { CLK portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "3.023 ns" { CLK CLK~out0 portcout:I_portcout|PortCOutRegQ[3] } { 0.000ns 0.000ns 1.653ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.023 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 3.023 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_M20 54 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 54; CLK Node = 'CLK'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "A8255.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/A8255.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.653 ns) + CELL(0.542 ns) 3.023 ns portcout:I_portcout\|PortCOutRegQ\[3\] 2 REG LC_X34_Y16_N1 7 " "Info: 2: + IC(1.653 ns) + CELL(0.542 ns) = 3.023 ns; Loc. = LC_X34_Y16_N1; Fanout = 7; REG Node = 'portcout:I_portcout\|PortCOutRegQ\[3\]'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.195 ns" { CLK portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "portcout.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/portcout.vhd" 388 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.32 % ) " "Info: Total cell delay = 1.370 ns ( 45.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.653 ns ( 54.68 % ) " "Info: Total interconnect delay = 1.653 ns ( 54.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.023 ns" { CLK portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "3.023 ns" { CLK CLK~out0 portcout:I_portcout|PortCOutRegQ[3] } { 0.000ns 0.000ns 1.653ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.023 ns" { CLK portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "3.023 ns" { CLK CLK~out0 portcout:I_portcout|PortCOutRegQ[3] } { 0.000ns 0.000ns 1.653ns } { 0.000ns 0.828ns 0.542ns } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.023 ns" { CLK portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "3.023 ns" { CLK CLK~out0 portcout:I_portcout|PortCOutRegQ[3] } { 0.000ns 0.000ns 1.653ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "portcout.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/portcout.vhd" 388 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "portcout.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/portcout.vhd" 388 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.577 ns" { portcout:I_portcout|PortCOutRegQ[3] portcout:I_portcout|PortCOutRegD[3]~6934 portcout:I_portcout|PortCOutRegD[3]~6935 portcout:I_portcout|PortCOutRegD[3]~6937 portcout:I_portcout|PortCOutRegD[3]~6938 portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "3.577 ns" { portcout:I_portcout|PortCOutRegQ[3] portcout:I_portcout|PortCOutRegD[3]~6934 portcout:I_portcout|PortCOutRegD[3]~6935 portcout:I_portcout|PortCOutRegD[3]~6937 portcout:I_portcout|PortCOutRegD[3]~6938 portcout:I_portcout|PortCOutRegQ[3] } { 0.000ns 1.101ns 0.487ns 0.964ns 0.134ns 0.506ns } { 0.000ns 0.075ns 0.075ns 0.075ns 0.075ns 0.085ns } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.023 ns" { CLK portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "3.023 ns" { CLK CLK~out0 portcout:I_portcout|PortCOutRegQ[3] } { 0.000ns 0.000ns 1.653ns } { 0.000ns 0.828ns 0.542ns } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.023 ns" { CLK portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "3.023 ns" { CLK CLK~out0 portcout:I_portcout|PortCOutRegQ[3] } { 0.000ns 0.000ns 1.653ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "portcout:I_portcout\|PortCOutRegQ\[3\] nCS CLK 7.786 ns register " "Info: tsu for register \"portcout:I_portcout\|PortCOutRegQ\[3\]\" (data pin = \"nCS\", clock pin = \"CLK\") is 7.786 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.799 ns + Longest pin register " "Info: + Longest pin to register delay is 10.799 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns nCS 1 PIN PIN_N3 9 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_N3; Fanout = 9; PIN Node = 'nCS'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { nCS } "NODE_NAME" } } { "A8255.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/A8255.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.807 ns) + CELL(0.183 ns) 6.224 ns cntl_log:I_cntl_log\|ControlLogicProc~70 2 COMB LC_X35_Y17_N3 8 " "Info: 2: + IC(4.807 ns) + CELL(0.183 ns) = 6.224 ns; Loc. = LC_X35_Y17_N3; Fanout = 8; COMB Node = 'cntl_log:I_cntl_log\|ControlLogicProc~70'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "4.990 ns" { nCS cntl_log:I_cntl_log|ControlLogicProc~70 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.290 ns) + CELL(0.280 ns) 7.794 ns cntl_log:I_cntl_log\|PortCOutLd\[3\]~858 3 COMB LC_X34_Y16_N8 2 " "Info: 3: + IC(1.290 ns) + CELL(0.280 ns) = 7.794 ns; Loc. = LC_X34_Y16_N8; Fanout = 2; COMB Node = 'cntl_log:I_cntl_log\|PortCOutLd\[3\]~858'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.570 ns" { cntl_log:I_cntl_log|ControlLogicProc~70 cntl_log:I_cntl_log|PortCOutLd[3]~858 } "NODE_NAME" } } { "cntl_log.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/cntl_log.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.549 ns) + CELL(0.183 ns) 8.526 ns cntl_log:I_cntl_log\|PortCOutLd\[3\]~859 4 COMB LC_X34_Y16_N6 2 " "Info: 4: + IC(0.549 ns) + CELL(0.183 ns) = 8.526 ns; Loc. = LC_X34_Y16_N6; Fanout = 2; COMB Node = 'cntl_log:I_cntl_log\|PortCOutLd\[3\]~859'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.732 ns" { cntl_log:I_cntl_log|PortCOutLd[3]~858 cntl_log:I_cntl_log|PortCOutLd[3]~859 } "NODE_NAME" } } { "cntl_log.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/cntl_log.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.529 ns) + CELL(0.075 ns) 9.130 ns portcout:I_portcout\|PortCOutRegD\[3\]~6933 5 COMB LC_X35_Y16_N8 1 " "Info: 5: + IC(0.529 ns) + CELL(0.075 ns) = 9.130 ns; Loc. = LC_X35_Y16_N8; Fanout = 1; COMB Node = 'portcout:I_portcout\|PortCOutRegD\[3\]~6933'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.604 ns" { cntl_log:I_cntl_log|PortCOutLd[3]~859 portcout:I_portcout|PortCOutRegD[3]~6933 } "NODE_NAME" } } { "portcout.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/portcout.vhd" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.798 ns) + CELL(0.280 ns) 10.208 ns portcout:I_portcout\|PortCOutRegD\[3\]~6938 6 COMB LC_X33_Y16_N9 1 " "Info: 6: + IC(0.798 ns) + CELL(0.280 ns) = 10.208 ns; Loc. = LC_X33_Y16_N9; Fanout = 1; COMB Node = 'portcout:I_portcout\|PortCOutRegD\[3\]~6938'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.078 ns" { portcout:I_portcout|PortCOutRegD[3]~6933 portcout:I_portcout|PortCOutRegD[3]~6938 } "NODE_NAME" } } { "portcout.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/portcout.vhd" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.506 ns) + CELL(0.085 ns) 10.799 ns portcout:I_portcout\|PortCOutRegQ\[3\] 7 REG LC_X34_Y16_N1 7 " "Info: 7: + IC(0.506 ns) + CELL(0.085 ns) = 10.799 ns; Loc. = LC_X34_Y16_N1; Fanout = 7; REG Node = 'portcout:I_portcout\|PortCOutRegQ\[3\]'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.591 ns" { portcout:I_portcout|PortCOutRegD[3]~6938 portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "portcout.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/portcout.vhd" 388 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.320 ns ( 21.48 % ) " "Info: Total cell delay = 2.320 ns ( 21.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.479 ns ( 78.52 % ) " "Info: Total interconnect delay = 8.479 ns ( 78.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "10.799 ns" { nCS cntl_log:I_cntl_log|ControlLogicProc~70 cntl_log:I_cntl_log|PortCOutLd[3]~858 cntl_log:I_cntl_log|PortCOutLd[3]~859 portcout:I_portcout|PortCOutRegD[3]~6933 portcout:I_portcout|PortCOutRegD[3]~6938 portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "10.799 ns" { nCS nCS~out0 cntl_log:I_cntl_log|ControlLogicProc~70 cntl_log:I_cntl_log|PortCOutLd[3]~858 cntl_log:I_cntl_log|PortCOutLd[3]~859 portcout:I_portcout|PortCOutRegD[3]~6933 portcout:I_portcout|PortCOutRegD[3]~6938 portcout:I_portcout|PortCOutRegQ[3] } { 0.000ns 0.000ns 4.807ns 1.290ns 0.549ns 0.529ns 0.798ns 0.506ns } { 0.000ns 1.234ns 0.183ns 0.280ns 0.183ns 0.075ns 0.280ns 0.085ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "portcout.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/portcout.vhd" 388 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.023 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 3.023 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_M20 54 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 54; CLK Node = 'CLK'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "A8255.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/A8255.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.653 ns) + CELL(0.542 ns) 3.023 ns portcout:I_portcout\|PortCOutRegQ\[3\] 2 REG LC_X34_Y16_N1 7 " "Info: 2: + IC(1.653 ns) + CELL(0.542 ns) = 3.023 ns; Loc. = LC_X34_Y16_N1; Fanout = 7; REG Node = 'portcout:I_portcout\|PortCOutRegQ\[3\]'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.195 ns" { CLK portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "portcout.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/portcout.vhd" 388 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.32 % ) " "Info: Total cell delay = 1.370 ns ( 45.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.653 ns ( 54.68 % ) " "Info: Total interconnect delay = 1.653 ns ( 54.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.023 ns" { CLK portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "3.023 ns" { CLK CLK~out0 portcout:I_portcout|PortCOutRegQ[3] } { 0.000ns 0.000ns 1.653ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "10.799 ns" { nCS cntl_log:I_cntl_log|ControlLogicProc~70 cntl_log:I_cntl_log|PortCOutLd[3]~858 cntl_log:I_cntl_log|PortCOutLd[3]~859 portcout:I_portcout|PortCOutRegD[3]~6933 portcout:I_portcout|PortCOutRegD[3]~6938 portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "10.799 ns" { nCS nCS~out0 cntl_log:I_cntl_log|ControlLogicProc~70 cntl_log:I_cntl_log|PortCOutLd[3]~858 cntl_log:I_cntl_log|PortCOutLd[3]~859 portcout:I_portcout|PortCOutRegD[3]~6933 portcout:I_portcout|PortCOutRegD[3]~6938 portcout:I_portcout|PortCOutRegQ[3] } { 0.000ns 0.000ns 4.807ns 1.290ns 0.549ns 0.529ns 0.798ns 0.506ns } { 0.000ns 1.234ns 0.183ns 0.280ns 0.183ns 0.075ns 0.280ns 0.085ns } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.023 ns" { CLK portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "3.023 ns" { CLK CLK~out0 portcout:I_portcout|PortCOutRegQ[3] } { 0.000ns 0.000ns 1.653ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}