{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 01 21:20:44 2008 " "Info: Processing started: Tue Apr 01 21:20:44 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A8255 -c A8255 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off A8255 -c A8255" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "A8255.vhd 2 1 " "Warning: Using design file A8255.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 a8255-structure " "Info: Found design unit 1: a8255-structure" {  } { { "A8255.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/A8255.vhd" 57 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 a8255 " "Info: Found entity 1: a8255" {  } { { "A8255.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/A8255.vhd" 32 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "A8255 " "Info: Elaborating entity \"A8255\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "dout_mux.vhd 2 1 " "Warning: Using design file dout_mux.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dout_mux-rtl " "Info: Found design unit 1: dout_mux-rtl" {  } { { "dout_mux.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/dout_mux.vhd" 47 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 dout_mux " "Info: Found entity 1: dout_mux" {  } { { "dout_mux.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/dout_mux.vhd" 32 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dout_mux dout_mux:I_dout_mux " "Info: Elaborating entity \"dout_mux\" for hierarchy \"dout_mux:I_dout_mux\"" {  } { { "A8255.vhd" "I_dout_mux" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/A8255.vhd" 187 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_GENERIC_WARNING_WITH_LOC" "sensitivity list already contains DOUTSelect dout_mux.vhd(50) " "Warning (10005): Verilog HDL or VHDL warning at dout_mux.vhd(50): sensitivity list already contains DOUTSelect" {  } { { "dout_mux.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/dout_mux.vhd" 50 0 0 } }  } 0 10005 "Verilog HDL or VHDL warning at %2!s!: %1!s!" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "cntl_log.vhd 2 1 " "Warning: Using design file cntl_log.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cntl_log-rtl " "Info: Found design unit 1: cntl_log-rtl" {  } { { "cntl_log.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/cntl_log.vhd" 61 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 cntl_log " "Info: Found entity 1: cntl_log" {  } { { "cntl_log.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/cntl_log.vhd" 33 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntl_log cntl_log:I_cntl_log " "Info: Elaborating entity \"cntl_log\" for hierarchy \"cntl_log:I_cntl_log\"" {  } { { "A8255.vhd" "I_cntl_log" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/A8255.vhd" 199 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "portaout.vhd 2 1 " "Warning: Using design file portaout.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 portaout-rtl " "Info: Found design unit 1: portaout-rtl" {  } { { "portaout.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/portaout.vhd" 44 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 portaout " "Info: Found entity 1: portaout" {  } { { "portaout.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/portaout.vhd" 32 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "portaout portaout:I_portaout " "Info: Elaborating entity \"portaout\" for hierarchy \"portaout:I_portaout\"" {  } { { "A8255.vhd" "I_portaout" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/A8255.vhd" 224 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "portain.vhd 2 1 " "Warning: Using design file portain.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 portain-rtl " "Info: Found design unit 1: portain-rtl" {  } { { "portain.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/portain.vhd" 44 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 portain " "Info: Found entity 1: portain" {  } { { "portain.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/portain.vhd" 32 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "portain portain:I_portain " "Info: Elaborating entity \"portain\" for hierarchy \"portain:I_portain\"" {  } { { "A8255.vhd" "I_portain" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/A8255.vhd" 234 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "portbout.vhd 2 1 " "Warning: Using design file portbout.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 portbout-rtl " "Info: Found design unit 1: portbout-rtl" {  } { { "portbout.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/portbout.vhd" 46 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 portbout " "Info: Found entity 1: portbout" {  } { { "portbout.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/portbout.vhd" 34 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "portbout portbout:I_portbout " "Info: Elaborating entity \"portbout\" for hierarchy \"portbout:I_portbout\"" {  } { { "A8255.vhd" "I_portbout" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/A8255.vhd" 243 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "portbin.vhd 2 1 " "Warning: Using design file portbin.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 portbin-rtl " "Info: Found design unit 1: portbin-rtl" {  } { { "portbin.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/portbin.vhd" 44 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 portbin " "Info: Found entity 1: portbin" {  } { { "portbin.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/portbin.vhd" 32 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "portbin portbin:I_portbin " "Info: Elaborating entity \"portbin\" for hierarchy \"portbin:I_portbin\"" {  } { { "A8255.vhd" "I_portbin" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/A8255.vhd" 252 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "portcout.vhd 2 1 " "Warning: Using design file portcout.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 portcout-rtl " "Info: Found design unit 1: portcout-rtl" {  } { { "portcout.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/portcout.vhd" 56 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 portcout " "Info: Found entity 1: portcout" {  } { { "portcout.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/portcout.vhd" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "portcout portcout:I_portcout " "Info: Elaborating entity \"portcout\" for hierarchy \"portcout:I_portcout\"" {  } { { "A8255.vhd" "I_portcout" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/A8255.vhd" 261 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "cntl_log.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/cntl_log.vhd" 220 -1 0 } } { "cntl_log.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/cntl_log.vhd" 220 -1 0 } } { "cntl_log.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/cntl_log.vhd" 220 -1 0 } } { "cntl_log.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/cntl_log.vhd" 220 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "247 " "Info: Implemented 247 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "39 " "Info: Implemented 39 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "42 " "Info: Implemented 42 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "166 " "Info: Implemented 166 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 9 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 01 21:20:52 2008 " "Info: Processing ended: Tue Apr 01 21:20:52 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}