?? frequency_div.vhdl
字號:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fdiv is
Generic ( rate : integer :=10 );
Port ( f_in : In std_logic;
f_out : Out std_logic );
end;
architecture behavioral of fdiv is
signal cnt : integer range 0 to rate := 0;
signal clk : std_logic:='0';
begin
process (f_in)
begin
if f_in'event and f_in = '1' then
if cnt /= rate then
cnt <= cnt + 1;
else
cnt <= 1;
clk<=not clk;
end if;
end if;
end process;
f_out <= clk;
end behavioral;
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