--written by Diao Lan Song
--1998/9/25

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.Std_logic_arith.all;

entity  Stimulus is
end  Stimulus;

architecture test_bench of Stimulus is

  component comp_DIVIDER
  port(
                  CLK_IN : in Std_logic;
                 RESET   : in Std_logic;
                 SPD : in Integer;
                 CLK_OUT :out Std_logic);
  end component;
  
   SIGNAL CLK_IN :  Std_logic;
   SIGNAL RESET   :  Std_logic;
   SIGNAL SPD  :  Integer;
   SIGNAL CLK_OUT : Std_logic;

  begin
    udut : comp_DIVIDER port map(CLK_IN,RESET,SPD,CLK_OUT);
    
    -- CLK_IN
    P_CLK_IN :
    process
    begin
       CLK_IN   <= '0';

       WHILE TRUE LOOP
           CLK_IN <= '1';
           WAIT FOR 10 ns;
           CLK_IN <= '0';                
           WAIT FOR 10 ns;
       END LOOP;
    end process P_CLK_IN;

  -- RESET
    P_RESET :
    process
    begin
      -- 0.000 
                        wait for 0.000 ns;      RESET <=  '1';
      -- 100.000 
                        wait for 100.000 ns;      RESET <=  '0';
      wait;
    end process;

  -- SPD
    P_SPD :
    process
    begin
      -- 0.000 
                        wait for 0.000 ns;      SPD <=  0;
      -- 1000.000 
                        wait for 1000.000 ns;      SPD <=  1;
      --2000.000
                        wait for 2000.000 ns;      SPD <=  2; 
                        wait for 3000.000 ns;      SPD <=  3; 
                        wait for 4000.000 ns;      SPD <=  4; 
                        wait for 5000.000 ns;      SPD <=  5; 
      wait;
   end process;

  
    EndProc :
    process
    begin
      wait for 10000 ns;
      ASSERT false REPORT "End of Simulation" SEVERITY error;
      wait;
    end process;
  end test_bench;

configuration DIVIDER_stim_conf of  Stimulus  is  
  for test_bench
    for udut : comp_DIVIDER use entity work.DIVIDER(RTL);
    end for;  
  end for;  
end DIVIDER_stim_conf;