-- Modified 4/19/2007-- Ian Rothlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;entity reggate is  port (	clk, reset_n : in std_logic;	input : in signed(31 downto 0);	enable : in std_logic;	output : out signed(31 downto 0)  );end reggate;architecture behavior of reggate isbegin  process (clk, reset_n, enable)  begin	if reset_n = '0' then	  output <= "00000000000000000000000000000000";	elsif clk'event and clk = '1' then	  if enable = '1' then	    output <= input;	  end if;	end if;  end process;end behavior;