SYSTEM system_0{   System_Wizard_Version = "6.10";   System_Wizard_Build = "201";   WIZARD_SCRIPT_ARGUMENTS    {      device_family = "CYCLONE";      clock_freq = "100000000";      generate_hdl = "1";      generate_sdk = "0";      do_build_sim = "0";      hardcopy_compatible = "0";      board_class = "DE2_Board";      CLOCKS       {         CLOCK clk         {            frequency = "100000000";            source = "External";            Is_Clock_Source = "0";            display_name = "clk";            pipeline = "0";         }         CLOCK clk_50         {            frequency = "50000000";            source = "External";            Is_Clock_Source = "0";            display_name = "clk_50";            pipeline = "0";         }      }      hdl_language = "verilog";      device_family_id = "CYCLONEII";      view_master_columns = "1";      view_master_priorities = "0";      name_column_width = "256";      desc_column_width = "257";      bustype_column_width = "0";      base_column_width = "75";      clock_column_width = "64";      end_column_width = "75";      BOARD_INFO       {         CONFIGURATION EPSC16         {            length = "";            menu_position = "1";            offset = "0x00000000";            reference_designator = "U30";         }         CONFIGURATION FLASH         {            length = "";            menu_position = "2";            offset = "0x00000000";            reference_designator = "U20";         }         JTAG_device_index = "1";         REFDES U20         {            base = "0x00100000";         }         REFDES U30         {            base = "0x00060000";         }         altera_avalon_cfi_flash          {            reference_designators = "U20";         }         altera_avalon_epcs_flash_controller          {            reference_designators = "U30";         }         class = "DE2_Board";         class_version = "1.0";         device_family = "CYCLONEII";         quartus_pgm_file = "system/DE2_Board.sof";         quartus_project_file = "system/DE2_Board.qpf";         reference_designators = "U30,U20";         sopc_system_file = "system/DE2_Board.ptf";      }      view_frame_window = "75:16:1063:956";      do_log_history = "0";   }   MODULE cpu_0   {      class = "altera_nios2";      class_version = "6.05";      iss_model_name = "altera_nios2";      HDL_INFO       {         PLI_Files = "";         Precompiled_Simulation_Library_Files = "";         Simulation_HDL_Files = "";         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/cpu_0_test_bench.v, __PROJECT_DIRECTORY__/cpu_0_mult_cell.v, __PROJECT_DIRECTORY__/cpu_0_jtag_debug_module.v, __PROJECT_DIRECTORY__/cpu_0_jtag_debug_module_wrapper.v, __PROJECT_DIRECTORY__/cpu_0.v";         Synthesis_Only_Files = "";      }      MASTER instruction_master      {         PORT_WIRING          {            PORT i_address            {               Is_Enabled = "1";               direction = "output";               type = "address";               width = "24";            }            PORT i_read            {               Is_Enabled = "1";               direction = "output";               type = "read";               width = "1";            }            PORT i_readdata            {               Is_Enabled = "1";               direction = "input";               type = "readdata";               width = "32";            }            PORT i_readdatavalid            {               Is_Enabled = "1";               direction = "input";               type = "readdatavalid";               width = "1";            }            PORT i_waitrequest            {               Is_Enabled = "1";               direction = "input";               type = "waitrequest";               width = "1";            }            PORT clk            {               Is_Enabled = "1";               direction = "input";               type = "clk";               width = "1";            }         }         SYSTEM_BUILDER_INFO          {            Bus_Type = "avalon";            Data_Width = "32";            Max_Address_Width = "31";            Address_Width = "8";            Is_Instruction_Master = "1";            Is_Readable = "1";            Is_Writeable = "0";            Address_Group = "0";            Has_IRQ = "0";            Irq_Scheme = "individual_requests";            Interrupt_Range = "0-0";            Is_Enabled = "1";            Maximum_Burst_Size = "1";            Burst_On_Burst_Boundaries_Only = "";            Linewrap_Bursts = "";            Interleave_Bursts = "";            Adapts_To = "";            Is_Big_Endian = "0";         }      }      MASTER tightly_coupled_instruction_master_0      {         PORT_WIRING          {         }         SYSTEM_BUILDER_INFO          {            Register_Incoming_Signals = "0";            Bus_Type = "avalon";            Data_Width = "32";            Max_Address_Width = "31";            Address_Width = "8";            Is_Instruction_Master = "1";            Has_IRQ = "0";            Is_Enabled = "0";            Connection_Limit = "1";            Is_Channel = "1";            Is_Big_Endian = "0";         }      }      MASTER tightly_coupled_instruction_master_1      {         PORT_WIRING          {         }         SYSTEM_BUILDER_INFO          {            Register_Incoming_Signals = "0";            Bus_Type = "avalon";            Data_Width = "32";            Max_Address_Width = "31";            Address_Width = "8";            Address_Group = "0";            Is_Instruction_Master = "1";            Is_Readable = "1";            Is_Writeable = "0";            Has_IRQ = "0";            Is_Enabled = "0";            Connection_Limit = "1";            Is_Channel = "1";            Is_Big_Endian = "0";         }      }      MASTER tightly_coupled_instruction_master_2      {         PORT_WIRING          {         }         SYSTEM_BUILDER_INFO          {            Register_Incoming_Signals = "0";            Bus_Type = "avalon";            Data_Width = "32";            Max_Address_Width = "31";            Address_Width = "8";            Address_Group = "0";            Is_Instruction_Master = "1";            Is_Readable = "1";            Is_Writeable = "0";            Has_IRQ = "0";            Is_Enabled = "0";            Connection_Limit = "1";            Is_Channel = "1";            Is_Big_Endian = "0";         }      }      MASTER tightly_coupled_instruction_master_3      {         PORT_WIRING          {         }         SYSTEM_BUILDER_INFO          {            Register_Incoming_Signals = "0";            Bus_Type = "avalon";            Data_Width = "32";            Max_Address_Width = "31";            Address_Width = "8";            Address_Group = "0";            Is_Instruction_Master = "1";            Is_Readable = "1";            Is_Writeable = "0";            Has_IRQ = "0";            Is_Enabled = "0";            Connection_Limit = "1";            Is_Channel = "1";            Is_Big_Endian = "0";         }      }      MASTER data_master      {         PORT_WIRING          {            PORT clk            {               Is_Enabled = "0";               direction = "input";               type = "clk";               width = "1";            }            PORT d_address            {               Is_Enabled = "1";               direction = "output";               type = "address";               width = "24";            }            PORT d_byteenable            {               Is_Enabled = "1";               direction = "output";               type = "byteenable";               width = "4";            }            PORT d_irq            {               Is_Enabled = "1";               direction = "input";               type = "irq";               width = "32";            }            PORT d_read            {               Is_Enabled = "1";               direction = "output";               type = "read";               width = "1";            }            PORT d_readdata            {               Is_Enabled = "1";               direction = "input";               type = "readdata";               width = "32";            }            PORT d_waitrequest            {               Is_Enabled = "1";               direction = "input";               type = "waitrequest";               width = "1";            }            PORT d_write            {               Is_Enabled = "1";               direction = "output";               type = "write";               width = "1";            }            PORT d_writedata            {               Is_Enabled = "1";               direction = "output";               type = "writedata";               width = "32";            }            PORT jtag_debug_module_debugaccess_to_roms            {               Is_Enabled = "1";               direction = "output";               type = "debugaccess";               width = "1";            }         }         SYSTEM_BUILDER_INFO          {            Register_Incoming_Signals = "1";            Bus_Type = "avalon";            Data_Width = "32";            Max_Address_Width = "31";            Address_Width = "8";            Address_Group = "0";            Is_Data_Master = "1";            Is_Readable = "1";            Is_Writeable = "1";            Has_IRQ = "1";            Irq_Scheme = "individual_requests";            Interrupt_Range = "0-31";            Is_Enabled = "1";            Maximum_Burst_Size = "1";            Burst_On_Burst_Boundaries_Only = "";            Adapts_To = "";            Is_Big_Endian = "0";         }      }      MASTER data_master2      {         PORT_WIRING          {         }         SYSTEM_BUILDER_INFO          {            Register_Incoming_Signals = "1";            Bus_Type = "avalon";            Data_Width = "32";            Max_Address_Width = "31";            Address_Width = "8";            Address_Group = "0";            Is_Data_Master = "1";            Is_Readable = "1";            Is_Writeable = "1";            Has_IRQ = "0";            Is_Enabled = "0";            Is_Big_Endian = "0";         }      }      MASTER tightly_coupled_data_master_0      {         PORT_WIRING          {         }         SYSTEM_BUILDER_INFO          {            Register_Incoming_Signals = "0";            Bus_Type = "avalon";            Data_Width = "32";            Max_Address_Width = "31";            Address_Width = "8";            Address_Group = "0";            Is_Data_Master = "1";            Is_Readable = "1";            Is_Writeable = "1";            Has_IRQ = "0";            Is_Enabled = "0";            Connection_Limit = "1";            Is_Channel = "1";            Is_Big_Endian = "0";         }      }      MASTER tightly_coupled_data_master_1      {         PORT_WIRING          {         }         SYSTEM_BUILDER_INFO          {            Register_Incoming_Signals = "0";            Bus_Type = "avalon";            Data_Width = "32";            Max_Address_Width = "31";            Address_Width = "8";            Address_Group = "0";            Is_Data_Master = "1";            Is_Readable = "1";            Is_Writeable = "1";            Has_IRQ = "0";            Is_Enabled = "0";            Connection_Limit = "1";            Is_Channel = "1";            Is_Big_Endian = "0";         }      }      MASTER tightly_coupled_data_master_2      {         PORT_WIRING          {         }         SYSTEM_BUILDER_INFO          {            Register_Incoming_Signals = "0";            Bus_Type = "avalon";            Data_Width = "32";            Max_Address_Width = "31";            Address_Width = "8";            Address_Group = "0";            Is_Data_Master = "1";            Is_Readable = "1";            Is_Writeable = "1";            Has_IRQ = "0";            Is_Enabled = "0";            Connection_Limit = "1";            Is_Channel = "1";            Is_Big_Endian = "0";         }      }      MASTER tightly_coupled_data_master_3      {         PORT_WIRING          {         }         SYSTEM_BUILDER_INFO          {            Register_Incoming_Signals = "0";            Bus_Type = "avalon";            Data_Width = "32";            Max_Address_Width = "31";            Address_Width = "8";            Address_Group = "0";            Is_Data_Master = "1";            Is_Readable = "1";            Is_Writeable = "1";            Has_IRQ = "0";            Is_Enabled = "0";            Connection_Limit = "1";