SIGNAL aad            {               format = "Logic";               name = "i_address";               radix = "hexadecimal";            }            SIGNAL aae            {               format = "Logic";               name = "i_read";               radix = "hexadecimal";            }            SIGNAL aaf            {               format = "Logic";               name = "clk";               radix = "hexadecimal";            }            SIGNAL aag            {               format = "Logic";               name = "reset_n";               radix = "hexadecimal";            }            SIGNAL aah            {               format = "Logic";               name = "d_readdata";               radix = "hexadecimal";            }            SIGNAL aai            {               format = "Logic";               name = "d_waitrequest";               radix = "hexadecimal";            }            SIGNAL aaj            {               format = "Logic";               name = "d_irq";               radix = "hexadecimal";            }            SIGNAL aak            {               format = "Logic";               name = "d_address";               radix = "hexadecimal";            }            SIGNAL aal            {               format = "Logic";               name = "d_byteenable";               radix = "hexadecimal";            }            SIGNAL aam            {               format = "Logic";               name = "d_read";               radix = "hexadecimal";            }            SIGNAL aan            {               format = "Logic";               name = "d_write";               radix = "hexadecimal";            }            SIGNAL aao            {               format = "Logic";               name = "d_writedata";               radix = "hexadecimal";            }            SIGNAL aap            {               format = "Divider";               name = "base pipeline";               radix = "";            }            SIGNAL aaq            {               format = "Logic";               name = "clk";               radix = "hexadecimal";            }            SIGNAL aar            {               format = "Logic";               name = "reset_n";               radix = "hexadecimal";            }            SIGNAL aas            {               format = "Logic";               name = "D_stall";               radix = "hexadecimal";            }            SIGNAL aat            {               format = "Logic";               name = "A_stall";               radix = "hexadecimal";            }            SIGNAL aau            {               format = "Logic";               name = "F_pcb_nxt";               radix = "hexadecimal";            }            SIGNAL aav            {               format = "Logic";               name = "F_pcb";               radix = "hexadecimal";            }            SIGNAL aaw            {               format = "Logic";               name = "D_pcb";               radix = "hexadecimal";            }            SIGNAL aax            {               format = "Logic";               name = "E_pcb";               radix = "hexadecimal";            }            SIGNAL aay            {               format = "Logic";               name = "M_pcb";               radix = "hexadecimal";            }            SIGNAL aaz            {               format = "Logic";               name = "A_pcb";               radix = "hexadecimal";            }            SIGNAL aba            {               format = "Logic";               name = "W_pcb";               radix = "hexadecimal";            }            SIGNAL abb            {               format = "Logic";               name = "F_vinst";               radix = "ascii";            }            SIGNAL abc            {               format = "Logic";               name = "D_vinst";               radix = "ascii";            }            SIGNAL abd            {               format = "Logic";               name = "E_vinst";               radix = "ascii";            }            SIGNAL abe            {               format = "Logic";               name = "M_vinst";               radix = "ascii";            }            SIGNAL abf            {               format = "Logic";               name = "A_vinst";               radix = "ascii";            }            SIGNAL abg            {               format = "Logic";               name = "W_vinst";               radix = "ascii";            }            SIGNAL abh            {               format = "Logic";               name = "F_inst_ram_hit";               radix = "hexadecimal";            }            SIGNAL abi            {               format = "Logic";               name = "F_issue";               radix = "hexadecimal";            }            SIGNAL abj            {               format = "Logic";               name = "F_kill";               radix = "hexadecimal";            }            SIGNAL abk            {               format = "Logic";               name = "D_kill";               radix = "hexadecimal";            }            SIGNAL abl            {               format = "Logic";               name = "D_refetch";               radix = "hexadecimal";            }            SIGNAL abm            {               format = "Logic";               name = "D_issue";               radix = "hexadecimal";            }            SIGNAL abn            {               format = "Logic";               name = "D_valid";               radix = "hexadecimal";            }            SIGNAL abo            {               format = "Logic";               name = "E_valid";               radix = "hexadecimal";            }            SIGNAL abp            {               format = "Logic";               name = "M_valid";               radix = "hexadecimal";            }            SIGNAL abq            {               format = "Logic";               name = "A_valid";               radix = "hexadecimal";            }            SIGNAL abr            {               format = "Logic";               name = "W_valid";               radix = "hexadecimal";            }            SIGNAL abs            {               format = "Logic";               name = "W_wr_dst_reg";               radix = "hexadecimal";            }            SIGNAL abt            {               format = "Logic";               name = "W_dst_regnum";               radix = "hexadecimal";            }            SIGNAL abu            {               format = "Logic";               name = "W_wr_data";               radix = "hexadecimal";            }            SIGNAL abv            {               format = "Logic";               name = "D_en";               radix = "hexadecimal";            }            SIGNAL abw            {               format = "Logic";               name = "E_en";               radix = "hexadecimal";            }            SIGNAL abx            {               format = "Logic";               name = "M_en";               radix = "hexadecimal";            }            SIGNAL aby            {               format = "Logic";               name = "A_en";               radix = "hexadecimal";            }            SIGNAL abz            {               format = "Logic";               name = "F_iw";               radix = "hexadecimal";            }            SIGNAL aca            {               format = "Logic";               name = "D_iw";               radix = "hexadecimal";            }            SIGNAL acb            {               format = "Logic";               name = "E_iw";               radix = "hexadecimal";            }            SIGNAL acc            {               format = "Logic";               name = "E_valid_prior_to_hbreak";               radix = "hexadecimal";            }            SIGNAL acd            {               format = "Logic";               name = "M_pipe_flush";               radix = "hexadecimal";            }            SIGNAL ace            {               format = "Logic";               name = "M_pipe_flush_baddr";               radix = "hexadecimal";            }            SIGNAL acf            {               format = "Logic";               name = "intr_req";               radix = "hexadecimal";            }            SIGNAL acg            {               format = "Logic";               name = "A_ienable_reg";               radix = "hexadecimal";            }            SIGNAL ach            {               format = "Logic";               name = "A_status_reg_pie";               radix = "hexadecimal";            }            SIGNAL aci            {               format = "Logic";               name = "E_valid_prior_to_hbreak";               radix = "hexadecimal";            }         }      }   }   MODULE tri_state_bridge_0   {      class = "altera_avalon_tri_state_bridge";      class_version = "6.05";      SLAVE avalon_slave      {         SYSTEM_BUILDER_INFO          {            Bus_Type = "avalon";            Bridges_To = "tristate_master";            Base_Address = "N/A";            Has_IRQ = "0";            IRQ = "N/A";            Register_Outgoing_Signals = "1";            Register_Incoming_Signals = "1";            MASTERED_BY cpu_0/instruction_master            {               priority = "1";            }            MASTERED_BY cpu_0/data_master            {               priority = "1";            }            IRQ_MASTER cpu_0/data_master            {               IRQ_Number = "NC";            }            Address_Group = "0";         }      }      MASTER tristate_master      {         SYSTEM_BUILDER_INFO          {            Bus_Type = "avalon_tristate";            Bridges_To = "avalon_slave";         }      }      SYSTEM_BUILDER_INFO       {         Instantiate_In_System_Module = "1";         Is_Enabled = "1";         Is_Bridge = "1";         Top_Level_Ports_Are_Enumerated = "1";         Clock_Source = "clk";         View          {            MESSAGES             {            }            Is_Collapsed = "1";         }      }      WIZARD_SCRIPT_ARGUMENTS       {      }   }   MODULE cfi_flash_0   {      class = "altera_avalon_cfi_flash";      class_version = "6.05";      iss_model_name = "altera_avalon_flash";      HDL_INFO       {      }      SLAVE s1      {         PORT_WIRING          {            PORT data            {               width = "8";               is_shared = "1";               direction = "inout";               type = "data";            }            PORT address            {               width = "22";               is_shared = "1";               direction = "input";               type = "address";            }            PORT read_n            {               width = "1";               is_shared = "1";               direction = "input";               type = "read_n";            }            PORT write_n            {               width = "1";               is_shared = "0";               direction = "input";               type = "write_n";            }            PORT select_n            {               width = "1";               is_shared = "0";               direction = "input";               type = "chipselect_n";            }         }         WIZARD_SCRIPT_ARGUMENTS          {            class = "altera_avalon_cfi_flash";            Supports_Flash_File_System = "1";            flash_reference_designator = "U20";         }