else if (s_chipselect & ~s_write_n & (s_address == 6'd02))
  const_alpha_lay2_reg <= s_writedata[5:0];

assign const_alpha_lay2 = const_alpha_lay2_reg[5:0];

always @(posedge clk_av or negedge reset_n)
 if (~reset_n)
  const_alpha_lay3_reg <= 6'b0;
 else if (s_chipselect & ~s_write_n & (s_address == 6'd03))
  const_alpha_lay3_reg <= s_writedata[5:0];

assign const_alpha_lay3 = const_alpha_lay3_reg[5:0];

always @(posedge clk_av or negedge reset_n)
 if (~reset_n)
  const_alpha_lay4_reg <= 6'b0;
 else if (s_chipselect & ~s_write_n & (s_address == 6'd04))
  const_alpha_lay4_reg <= s_writedata[5:0];

assign const_alpha_lay4 = const_alpha_lay4_reg[5:0];

always @(posedge clk_av or negedge reset_n)
 if (~reset_n)
  background_reg <= 16'hfa88; //power-up value of deep blue
 else if (s_chipselect & ~s_write_n & (s_address == 6'd05))
  background_reg <= s_writedata[15:0];

assign background = background_reg[15:0];

always @(posedge clk_av or negedge reset_n)
 if (~reset_n)
  win_l1_h_start_reg <= 12'b0;
 else if (s_chipselect & ~s_write_n & (s_address == 6'd06))
  win_l1_h_start_reg <= s_writedata[11:0];

assign win_l1_h_start = win_l1_h_start_reg[11:0];

always @(posedge clk_av or negedge reset_n)
 if (~reset_n)
  win_l1_h_stop_reg <= 12'b0;
 else if (s_chipselect & ~s_write_n & (s_address == 6'd07))
  win_l1_h_stop_reg <= s_writedata[11:0];

assign win_l1_h_stop = win_l1_h_stop_reg[11:0];

always @(posedge clk_av or negedge reset_n)
 if (~reset_n)
  win_l1_v_start_reg <= 12'b0;
 else if (s_chipselect & ~s_write_n & (s_address == 6'd08))
  win_l1_v_start_reg <= s_writedata[11:0];

assign win_l1_v_start = win_l1_v_start_reg[11:0];

always @(posedge clk_av or negedge reset_n)
 if (~reset_n)
  win_l1_v_stop_reg <= 12'b0;
 else if (s_chipselect & ~s_write_n & (s_address == 6'd09))
  win_l1_v_stop_reg <= s_writedata[11:0];

assign win_l1_v_stop = win_l1_v_stop_reg[11:0];

always @(posedge clk_av or negedge reset_n)
 if (~reset_n)
  win_l2_h_start_reg <= 12'b0;
 else if (s_chipselect & ~s_write_n & (s_address == 6'd10))
  win_l2_h_start_reg <= s_writedata[11:0];

assign win_l2_h_start = win_l2_h_start_reg[11:0];

always @(posedge clk_av or negedge reset_n)
 if (~reset_n)
  win_l2_h_stop_reg <= 12'b0;
 else if (s_chipselect & ~s_write_n & (s_address == 6'd11))
  win_l2_h_stop_reg <= s_writedata[11:0];

assign win_l2_h_stop = win_l2_h_stop_reg[11:0];

always @(posedge clk_av or negedge reset_n)
 if (~reset_n)
  win_l2_v_start_reg <= 12'b0;
 else if (s_chipselect & ~s_write_n & (s_address == 6'd12))
  win_l2_v_start_reg <= s_writedata[11:0];

assign win_l2_v_start = win_l2_v_start_reg[11:0];

always @(posedge clk_av or negedge reset_n)
 if (~reset_n)
  win_l2_v_stop_reg <= 12'b0;
 else if (s_chipselect & ~s_write_n & (s_address == 6'd13))
  win_l2_v_stop_reg <= s_writedata[11:0];

assign win_l2_v_stop = win_l2_v_stop_reg[11:0];

always @(posedge clk_av or negedge reset_n)
 if (~reset_n)
  win_l3_h_start_reg <= 12'b0;
 else if (s_chipselect & ~s_write_n & (s_address == 6'd14))
  win_l3_h_start_reg <= s_writedata[11:0];

assign win_l3_h_start = win_l3_h_start_reg[11:0];

always @(posedge clk_av or negedge reset_n)
 if (~reset_n)
  win_l3_h_stop_reg <= 12'b0;
 else if (s_chipselect & ~s_write_n & (s_address == 6'd15))
  win_l3_h_stop_reg <= s_writedata[11:0];

assign win_l3_h_stop = win_l3_h_stop_reg[11:0];

always @(posedge clk_av or negedge reset_n)
 if (~reset_n)
  win_l3_v_start_reg <= 12'b0;
 else if (s_chipselect & ~s_write_n & (s_address == 6'd16))
  win_l3_v_start_reg <= s_writedata[11:0];

assign win_l3_v_start = win_l3_v_start_reg[11:0];

always @(posedge clk_av or negedge reset_n)
 if (~reset_n)
  win_l3_v_stop_reg <= 12'b0;
 else if (s_chipselect & ~s_write_n & (s_address == 6'd17))
  win_l3_v_stop_reg <= s_writedata[11:0];

assign win_l3_v_stop = win_l3_v_stop_reg[11:0];

always @(posedge clk_av or negedge reset_n)
 if (~reset_n)
  win_l4_h_start_reg <= 12'b0;
 else if (s_chipselect & ~s_write_n & (s_address == 6'd18))
  win_l4_h_start_reg <= s_writedata[11:0];

assign win_l4_h_start = win_l4_h_start_reg[11:0];

always @(posedge clk_av or negedge reset_n)
 if (~reset_n)
  win_l4_h_stop_reg <= 12'b0;
 else if (s_chipselect & ~s_write_n & (s_address == 6'd19))
  win_l4_h_stop_reg <= s_writedata[11:0];

assign win_l4_h_stop = win_l4_h_stop_reg[11:0];

always @(posedge clk_av or negedge reset_n)
 if (~reset_n)
  win_l4_v_start_reg <= 12'b0;
 else if (s_chipselect & ~s_write_n & (s_address == 6'd20))
  win_l4_v_start_reg <= s_writedata[11:0];

assign win_l4_v_start = win_l4_v_start_reg[11:0];

always @(posedge clk_av or negedge reset_n)
 if (~reset_n)
  win_l4_v_stop_reg <= 12'b0;
 else if (s_chipselect & ~s_write_n & (s_address == 6'd21))
  win_l4_v_stop_reg <= s_writedata[11:0];

assign win_l4_v_stop = win_l4_v_stop_reg[11:0];


always @(posedge clk_av or negedge reset_n)
 if (~reset_n)
  layer_0_dma_start_addr_reg <= 32'b0;
 else if (s_chipselect & ~s_write_n & (s_address == 6'd22))
  layer_0_dma_start_addr_reg <= s_writedata;

assign layer_0_dma_start_addr = layer_0_dma_start_addr_reg;

always @(posedge clk_av or negedge reset_n)
 if (~reset_n)
  layer_0_dma_length_reg <= 32'b0;
 else if (s_chipselect & ~s_write_n & (s_address == 6'd23))
  layer_0_dma_length_reg <= s_writedata;

assign layer_0_dma_length = layer_0_dma_length_reg;

always @(posedge clk_av or negedge reset_n)
 if (~reset_n)
  layer_1_dma_start_addr_reg <= 32'b0;
 else if (s_chipselect & ~s_write_n & (s_address == 6'd24))
  layer_1_dma_start_addr_reg <= s_writedata;

assign layer_1_dma_start_addr = layer_1_dma_start_addr_reg;

always @(posedge clk_av or negedge reset_n)
 if (~reset_n)
  layer_1_dma_length_reg <= 32'b0;
 else if (s_chipselect & ~s_write_n & (s_address == 6'd25))
  layer_1_dma_length_reg <= s_writedata;

assign layer_1_dma_length = layer_1_dma_length_reg;

always @(posedge clk_av or negedge reset_n)
 if (~reset_n)
  layer_2_dma_start_addr_reg <= 32'b0;
 else if (s_chipselect & ~s_write_n & (s_address == 6'd26))
  layer_2_dma_start_addr_reg <= s_writedata;

assign layer_2_dma_start_addr = layer_2_dma_start_addr_reg;

always @(posedge clk_av or negedge reset_n)
 if (~reset_n)
  layer_2_dma_length_reg <= 32'b0;
 else if (s_chipselect & ~s_write_n & (s_address == 6'd27))
  layer_2_dma_length_reg <= s_writedata;

assign layer_2_dma_length = layer_2_dma_length_reg;

always @(posedge clk_av or negedge reset_n)
 if (~reset_n)
  layer_3_dma_start_addr_reg <= 32'b0;
 else if (s_chipselect & ~s_write_n & (s_address == 6'd28))
  layer_3_dma_start_addr_reg <= s_writedata;

assign layer_3_dma_start_addr = layer_3_dma_start_addr_reg;

always @(posedge clk_av or negedge reset_n)
 if (~reset_n)
  layer_3_dma_length_reg <= 32'b0;
 else if (s_chipselect & ~s_write_n & (s_address == 6'd29))
  layer_3_dma_length_reg <= s_writedata;

assign layer_3_dma_length = layer_3_dma_length_reg;

always @(posedge clk_av or negedge reset_n)
 if (~reset_n)
  layer_4_dma_start_addr_reg <= 32'b0;
 else if (s_chipselect & ~s_write_n & (s_address == 6'd30))
  layer_4_dma_start_addr_reg <= s_writedata;

assign layer_4_dma_start_addr = layer_4_dma_start_addr_reg;

always @(posedge clk_av or negedge reset_n)
 if (~reset_n)
  layer_4_dma_length_reg <= 32'b0;
 else if (s_chipselect & ~s_write_n & (s_address == 6'd31))
  layer_4_dma_length_reg <= s_writedata;

assign layer_4_dma_length = layer_4_dma_length_reg;

always @(posedge clk_av or negedge reset_n)
 if (~reset_n)
  dma_control_reg <= 5'b0;
 else if (s_chipselect & ~s_write_n & (s_address == 6'd32))
  dma_control_reg <= s_writedata[4:0];

assign dma_layer_0_on = dma_control_reg[0];
assign dma_layer_1_on = dma_control_reg[1];
assign dma_layer_2_on = dma_control_reg[2];
assign dma_layer_3_on = dma_control_reg[3];
assign dma_layer_4_on = dma_control_reg[4];

always@(layer_0_on or layer_1_on or layer_2_on or layer_3_on or layer_4_on or vblank)
 begin
  status_reg[0] = layer_0_on;
  status_reg[1] = layer_1_on;
  status_reg[2] = layer_2_on;
  status_reg[3] = layer_3_on;
  status_reg[4] = layer_4_on;
  status_reg[7:5] = 'b0;
  status_reg[8] = vblank;
  status_reg[31:9] = 'b0;
 end

always @(s_chipselect or s_read_n or s_address or status_reg or const_alpha_lay1_reg or const_alpha_lay2_reg
         or const_alpha_lay3_reg or const_alpha_lay4_reg or background_reg
         or win_l1_h_start_reg or win_l1_h_stop_reg or win_l1_v_start_reg or win_l1_v_stop_reg
         or win_l2_h_start_reg or win_l2_h_stop_reg or win_l2_v_start_reg or win_l2_v_stop_reg
         or win_l3_h_start_reg or win_l3_h_stop_reg or win_l3_v_start_reg or win_l3_v_stop_reg
         or win_l4_h_start_reg or win_l4_h_stop_reg or win_l4_v_start_reg or win_l4_v_stop_reg
         or layer_0_dma_start_addr_reg or layer_0_dma_length_reg
         or layer_1_dma_start_addr_reg or layer_1_dma_length_reg
         or layer_2_dma_start_addr_reg or layer_2_dma_length_reg
         or layer_3_dma_start_addr_reg or layer_3_dma_length_reg
         or layer_4_dma_start_addr_reg or layer_4_dma_length_reg
         or dma_control_reg or int_enable_reg or int_status_reg
         )
if (s_chipselect & ~s_read_n)
 case (s_address)
  6'd0: s_readdata = status_reg;
  6'd1: s_readdata = {26'b0, const_alpha_lay1_reg};
  6'd2: s_readdata = {26'b0, const_alpha_lay2_reg};
  6'd3: s_readdata = {26'b0, const_alpha_lay3_reg};
  6'd4: s_readdata = {26'b0, const_alpha_lay4_reg};
  6'd5: s_readdata = {16'b0, background_reg};
  6'd6: s_readdata = {20'b0, win_l1_h_start_reg};
  6'd7: s_readdata = {20'b0, win_l1_h_stop_reg};
  6'd8: s_readdata = {20'b0, win_l1_v_start_reg};
  6'd9: s_readdata = {20'b0, win_l1_v_stop_reg};
  6'd10: s_readdata = {20'b0, win_l2_h_start_reg};
  6'd11: s_readdata = {20'b0, win_l2_h_stop_reg};
  6'd12: s_readdata = {20'b0, win_l2_v_start_reg};
  6'd13: s_readdata = {20'b0, win_l2_v_stop_reg};
  6'd14: s_readdata = {20'b0, win_l3_h_start_reg};
  6'd15: s_readdata = {20'b0, win_l3_h_stop_reg};
  6'd16: s_readdata = {20'b0, win_l3_v_start_reg};
  6'd17: s_readdata = {20'b0, win_l3_v_stop_reg};
  6'd18: s_readdata = {20'b0, win_l4_h_start_reg};
  6'd19: s_readdata = {20'b0, win_l4_h_stop_reg};
  6'd20: s_readdata = {20'b0, win_l4_v_start_reg};
  6'd21: s_readdata = {20'b0, win_l4_v_stop_reg};
  6'd22: s_readdata = layer_0_dma_start_addr_reg;
  6'd23: s_readdata = layer_0_dma_length_reg;
  6'd24: s_readdata = layer_1_dma_start_addr_reg;
  6'd25: s_readdata = layer_1_dma_length_reg;
  6'd26: s_readdata = layer_2_dma_start_addr_reg;
  6'd27: s_readdata = layer_2_dma_length_reg;
  6'd28: s_readdata = layer_3_dma_start_addr_reg;
  6'd29: s_readdata = layer_3_dma_length_reg;
  6'd30: s_readdata = layer_4_dma_start_addr_reg;
  6'd31: s_readdata = layer_4_dma_length_reg;
  6'd32: s_readdata = {27'b0, dma_control_reg};
  6'd33: s_readdata = {31'b0, int_enable_reg};
  6'd34: s_readdata = {31'b0, int_status_reg};
  default: s_readdata = status_reg;
 endcase
else
 s_readdata = status_reg;

//Register Bank - END


endmodule