// ================================================================================
// (c) 2004 Altera Corporation. All rights reserved.
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// rights, copyrights and other intellectual property laws.
// 
// This reference design file, and your use thereof, is subject to and governed
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// ================================================================================


module DPath (
//inputs
pixel_clk,
layer0,
layer1,
layer2,
layer3,
layer4,
alpha_l1,
alpha_l2,
alpha_l3,
alpha_l4,
alpha_l1_max,
alpha_l2_max,
alpha_l3_max,
alpha_l4_max,
//outputs
result
);

//inputs
input pixel_clk;
input [5:0] layer0;
input [5:0] layer1;
input [5:0] layer2;
input [5:0] layer3;
input [5:0] layer4;
input [5:0] alpha_l1;
input [5:0] alpha_l2;
input [5:0] alpha_l3;
input [5:0] alpha_l4;
input alpha_l1_max;
input alpha_l2_max;
input alpha_l3_max;
input alpha_l4_max;

//outputs
output [5:0] result;

//wires
wire [5:0] layer0_1;
wire [5:0] layer0_1_2;
wire [5:0] layer0_1_2_3;
wire [5:0] layer0_1_2_3_4;

blender u_l1_l0 (
.pixel_clk (pixel_clk),
.layer_1 (layer1),
.layer_0 (layer0),
.alpha (alpha_l1),
.result (layer0_1)
	);

reg [5:0] layer1_reg;
always @(posedge pixel_clk)
 begin
  layer1_reg <= layer1;
 end

wire [5:0] layer0_1_next;
assign layer0_1_next = alpha_l1_max ? layer1_reg : layer0_1;

blender u_l2_l1_l0 (
.pixel_clk (pixel_clk),
.layer_1 (layer2),
.layer_0 (layer0_1_next),
.alpha (alpha_l2),
.result (layer0_1_2)
	);

reg [5:0] layer2_reg;
always @(posedge pixel_clk)
 layer2_reg <= layer2;

wire [5:0] layer0_1_2_next;
assign layer0_1_2_next = alpha_l2_max ? layer2_reg : layer0_1_2;

blender u_l3_l2_l1_l0 (
.pixel_clk (pixel_clk),
.layer_1 (layer3),
.layer_0 (layer0_1_2_next),
.alpha (alpha_l3),
.result (layer0_1_2_3)
	);

reg [5:0] layer3_reg;
always @(posedge pixel_clk)
 layer3_reg <= layer3;

wire [5:0] layer0_1_2_3_next;
assign layer0_1_2_3_next = alpha_l3_max ? layer3_reg : layer0_1_2_3;

blender u_l4_l3_l2_l1_l0 (
.pixel_clk (pixel_clk),
.layer_1 (layer4),
.layer_0 (layer0_1_2_3_next),
.alpha (alpha_l4),
.result (layer0_1_2_3_4)
	);

reg [5:0] layer4_reg;
always @(posedge pixel_clk)
 begin
  layer4_reg <= layer4;
 end

assign result = alpha_l4_max ? layer4_reg : layer0_1_2_3_4;

endmodule