vendor_name = ModelSim
source_file = 1, E:/電子設計競賽/verilog/62256接口/inter62256.v
source_file = 1, E:/電子設計競賽/verilog/62256接口/62256.vwf
source_file = 1, E:/電子設計競賽/verilog/62256接口/Waveform1.vwf
design_name = inter62256
instance = comp, \data_io[0]~I , data_io[0], inter62256, 1
instance = comp, \data_io[1]~I , data_io[1], inter62256, 1
instance = comp, \data_io[2]~I , data_io[2], inter62256, 1
instance = comp, \data_io[3]~I , data_io[3], inter62256, 1
instance = comp, \data_io[4]~I , data_io[4], inter62256, 1
instance = comp, \data_io[5]~I , data_io[5], inter62256, 1
instance = comp, \data_io[6]~I , data_io[6], inter62256, 1
instance = comp, \data_io[7]~I , data_io[7], inter62256, 1
instance = comp, \clk~I , clk, inter62256, 1
instance = comp, \rst~I , rst, inter62256, 1
instance = comp, \CS~reg0_I , CS~reg0, inter62256, 1
instance = comp, \mode~I , mode, inter62256, 1
instance = comp, \read_en~I , read_en, inter62256, 1
instance = comp, \read_en0~I , read_en0, inter62256, 1
instance = comp, \read_en1~I , read_en1, inter62256, 1
instance = comp, \addr[9]~1360_I , addr[9]~1360, inter62256, 1
instance = comp, \addr_in[7]~I , addr_in[7], inter62256, 1
instance = comp, \addr_in[6]~I , addr_in[6], inter62256, 1
instance = comp, \write_en~I , write_en, inter62256, 1
instance = comp, \write_en0~I , write_en0, inter62256, 1
instance = comp, \write_en1~I , write_en1, inter62256, 1
instance = comp, \always0~0_I , always0~0, inter62256, 1
instance = comp, \Add0~236_I , Add0~236, inter62256, 1
instance = comp, \Add0~238_I , Add0~238, inter62256, 1
instance = comp, \addr[7]~1362_I , addr[7]~1362, inter62256, 1
instance = comp, \addr[9]~1375_I , addr[9]~1375, inter62256, 1
instance = comp, \addr[9]~1376_I , addr[9]~1376, inter62256, 1
instance = comp, \data_in_temp[0]~274_I , data_in_temp[0]~274, inter62256, 1
instance = comp, \addr[7]~1365_I , addr[7]~1365, inter62256, 1
instance = comp, \addr[7]~1366_I , addr[7]~1366, inter62256, 1
instance = comp, \OE~187_I , OE~187, inter62256, 1
instance = comp, \addr[7]~1367_I , addr[7]~1367, inter62256, 1
instance = comp, \addr[8]~reg0_I , addr[8]~reg0, inter62256, 1
instance = comp, \addr_in[2]~I , addr_in[2], inter62256, 1
instance = comp, \addr_in[1]~I , addr_in[1], inter62256, 1
instance = comp, \addr_in[0]~I , addr_in[0], inter62256, 1
instance = comp, \Add0~222_I , Add0~222, inter62256, 1
instance = comp, \addr[7]~1361_I , addr[7]~1361, inter62256, 1
instance = comp, \addr[0]~reg0_I , addr[0]~reg0, inter62256, 1
instance = comp, \Add0~224_I , Add0~224, inter62256, 1
instance = comp, \addr[1]~reg0_I , addr[1]~reg0, inter62256, 1
instance = comp, \Add0~226_I , Add0~226, inter62256, 1
instance = comp, \addr[2]~reg0_I , addr[2]~reg0, inter62256, 1
instance = comp, \addr_in[3]~I , addr_in[3], inter62256, 1
instance = comp, \Add0~228_I , Add0~228, inter62256, 1
instance = comp, \addr[3]~reg0_I , addr[3]~reg0, inter62256, 1
instance = comp, \Equal0~129_I , Equal0~129, inter62256, 1
instance = comp, \addr_in[5]~I , addr_in[5], inter62256, 1
instance = comp, \addr_in[4]~I , addr_in[4], inter62256, 1
instance = comp, \Add0~230_I , Add0~230, inter62256, 1
instance = comp, \addr[4]~reg0_I , addr[4]~reg0, inter62256, 1
instance = comp, \Add0~232_I , Add0~232, inter62256, 1
instance = comp, \addr[5]~reg0_I , addr[5]~reg0, inter62256, 1
instance = comp, \Equal0~130_I , Equal0~130, inter62256, 1
instance = comp, \Add0~240_I , Add0~240, inter62256, 1
instance = comp, \addr[9]~reg0_I , addr[9]~reg0, inter62256, 1
instance = comp, \Add0~242_I , Add0~242, inter62256, 1
instance = comp, \addr[10]~reg0_I , addr[10]~reg0, inter62256, 1
instance = comp, \Add0~244_I , Add0~244, inter62256, 1
instance = comp, \addr[11]~reg0_I , addr[11]~reg0, inter62256, 1
instance = comp, \Add0~246_I , Add0~246, inter62256, 1
instance = comp, \addr[12]~reg0_I , addr[12]~reg0, inter62256, 1
instance = comp, \Add0~248_I , Add0~248, inter62256, 1
instance = comp, \addr[13]~reg0_I , addr[13]~reg0, inter62256, 1
instance = comp, \Add0~250_I , Add0~250, inter62256, 1
instance = comp, \addr[14]~reg0_I , addr[14]~reg0, inter62256, 1
instance = comp, \Equal1~188_I , Equal1~188, inter62256, 1
instance = comp, \Equal1~189_I , Equal1~189, inter62256, 1
instance = comp, \Equal0~131_I , Equal0~131, inter62256, 1
instance = comp, \write~I , write, inter62256, 1
instance = comp, \WE_hold[1]~I , WE_hold[1], inter62256, 1
instance = comp, \write_clk~I , write_clk, inter62256, 1
instance = comp, \write_clk0~I , write_clk0, inter62256, 1
instance = comp, \write_clk1~I , write_clk1, inter62256, 1
instance = comp, \drop~23_I , drop~23, inter62256, 1
instance = comp, \drop~I , drop, inter62256, 1
instance = comp, \WE_hold~38_I , WE_hold~38, inter62256, 1
instance = comp, \WE_hold~39_I , WE_hold~39, inter62256, 1
instance = comp, \WE_hold[0]~I , WE_hold[0], inter62256, 1
instance = comp, \addr[7]~1384_I , addr[7]~1384, inter62256, 1
instance = comp, \addr[7]~1363_I , addr[7]~1363, inter62256, 1
instance = comp, \Add0~234_I , Add0~234, inter62256, 1
instance = comp, \addr[6]~reg0_I , addr[6]~reg0, inter62256, 1
instance = comp, \addr[7]~reg0_I , addr[7]~reg0, inter62256, 1
instance = comp, \Add1~124_I , Add1~124, inter62256, 1
instance = comp, \Add1~114_I , Add1~114, inter62256, 1
instance = comp, \Add1~118_I , Add1~118, inter62256, 1
instance = comp, \Add1~126_I , Add1~126, inter62256, 1
instance = comp, \Add1~122_I , Add1~122, inter62256, 1
instance = comp, \Add1~116_I , Add1~116, inter62256, 1
instance = comp, \Equal1~190_I , Equal1~190, inter62256, 1
instance = comp, \Equal1~191_I , Equal1~191, inter62256, 1
instance = comp, \Equal1~193_I , Equal1~193, inter62256, 1
instance = comp, \Add1~120_I , Add1~120, inter62256, 1
instance = comp, \Equal1~192_I , Equal1~192, inter62256, 1
instance = comp, \Equal1~194_I , Equal1~194, inter62256, 1
instance = comp, \Equal1~195_I , Equal1~195, inter62256, 1
instance = comp, \always0~3_I , always0~3, inter62256, 1
instance = comp, \OE~185_I , OE~185, inter62256, 1
instance = comp, \OE~186_I , OE~186, inter62256, 1
instance = comp, \OE~reg0_I , OE~reg0, inter62256, 1
instance = comp, \WE~656_I , WE~656, inter62256, 1
instance = comp, \WE~reg0_I , WE~reg0, inter62256, 1
instance = comp, \mod~I , mod, inter62256, 1
instance = comp, \data_in[0]~I , data_in[0], inter62256, 1
instance = comp, \WE~658_I , WE~658, inter62256, 1
instance = comp, \WE~659_I , WE~659, inter62256, 1
instance = comp, \read~I , read, inter62256, 1
instance = comp, \data_temp[0]~I , data_temp[0], inter62256, 1
instance = comp, \data_in_temp[0]~275_I , data_in_temp[0]~275, inter62256, 1
instance = comp, \data_in_temp[0]~I , data_in_temp[0], inter62256, 1
instance = comp, \data_in[1]~I , data_in[1], inter62256, 1
instance = comp, \data_temp[1]~I , data_temp[1], inter62256, 1
instance = comp, \data_in_temp[1]~I , data_in_temp[1], inter62256, 1
instance = comp, \data_in[2]~I , data_in[2], inter62256, 1
instance = comp, \data_temp[2]~I , data_temp[2], inter62256, 1
instance = comp, \data_in_temp[2]~I , data_in_temp[2], inter62256, 1
instance = comp, \data_in[3]~I , data_in[3], inter62256, 1
instance = comp, \data_temp[3]~I , data_temp[3], inter62256, 1
instance = comp, \data_in_temp[3]~I , data_in_temp[3], inter62256, 1
instance = comp, \data_in[4]~I , data_in[4], inter62256, 1
instance = comp, \data_temp[4]~I , data_temp[4], inter62256, 1
instance = comp, \data_in_temp[4]~I , data_in_temp[4], inter62256, 1
instance = comp, \data_in[5]~I , data_in[5], inter62256, 1
instance = comp, \data_temp[5]~I , data_temp[5], inter62256, 1
instance = comp, \data_in_temp[5]~I , data_in_temp[5], inter62256, 1
instance = comp, \data_in[6]~I , data_in[6], inter62256, 1
instance = comp, \data_temp[6]~I , data_temp[6], inter62256, 1
instance = comp, \data_in_temp[6]~I , data_in_temp[6], inter62256, 1
instance = comp, \data_in[7]~I , data_in[7], inter62256, 1
instance = comp, \data_temp[7]~I , data_temp[7], inter62256, 1
instance = comp, \data_in_temp[7]~I , data_in_temp[7], inter62256, 1
instance = comp, \req~138_I , req~138, inter62256, 1
instance = comp, \req~139_I , req~139, inter62256, 1
instance = comp, \req~140_I , req~140, inter62256, 1
instance = comp, \req~reg0_I , req~reg0, inter62256, 1
instance = comp, \CS~I , CS, inter62256, 1
instance = comp, \OE~I , OE, inter62256, 1
instance = comp, \WE~I , WE, inter62256, 1
instance = comp, \addr[0]~I , addr[0], inter62256, 1
instance = comp, \addr[1]~I , addr[1], inter62256, 1
instance = comp, \addr[2]~I , addr[2], inter62256, 1
instance = comp, \addr[3]~I , addr[3], inter62256, 1
instance = comp, \addr[4]~I , addr[4], inter62256, 1
instance = comp, \addr[5]~I , addr[5], inter62256, 1
instance = comp, \addr[6]~I , addr[6], inter62256, 1
instance = comp, \addr[7]~I , addr[7], inter62256, 1
instance = comp, \addr[8]~I , addr[8], inter62256, 1
instance = comp, \addr[9]~I , addr[9], inter62256, 1
instance = comp, \addr[10]~I , addr[10], inter62256, 1
instance = comp, \addr[11]~I , addr[11], inter62256, 1
instance = comp, \addr[12]~I , addr[12], inter62256, 1
instance = comp, \addr[13]~I , addr[13], inter62256, 1
instance = comp, \addr[14]~I , addr[14], inter62256, 1
instance = comp, \data_out[0]~I , data_out[0], inter62256, 1
instance = comp, \data_out[1]~I , data_out[1], inter62256, 1
instance = comp, \data_out[2]~I , data_out[2], inter62256, 1
instance = comp, \data_out[3]~I , data_out[3], inter62256, 1
instance = comp, \data_out[4]~I , data_out[4], inter62256, 1
instance = comp, \data_out[5]~I , data_out[5], inter62256, 1
instance = comp, \data_out[6]~I , data_out[6], inter62256, 1
instance = comp, \data_out[7]~I , data_out[7], inter62256, 1
instance = comp, \req~I , req, inter62256, 1