前段時間看見有人在網上求并串轉換的程序，今天閑了，就編了一個供大家參考一下。
其實是很簡單的，只要理清思路，還是很容易的 。


程序編完之后，仔細回頭看看，
 發現其實里面還有一些端口什么的可以省略的，但是既然已經費這么長的時間編寫完了，也就不再修改了，如果
大家覺得比較繁瑣的話可以自己在此基礎上做出修改的，呵呵 我回去了。祝大家天天好心情。



并串轉換（16--1）

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity p2s16_1 is
    Port ( reset : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           start : in  STD_LOGIC;
           data_in : in  STD_LOGIC_VECTOR (15 downto 0);
           data_valid : out  STD_LOGIC;
           ready : out  STD_LOGIC;
           q : out  STD_LOGIC);
end p2s16_1;

architecture Behavioral of p2s16_1 is
signal reg : std_logic_vector(15 downto 0);
signal cnt : std_logic_vector(4 downto 0);
signal reg_en : std_logic;
signal shift_start : std_logic;
type state is (idle,recieve,shift,finish);
signal current_state, next_state : state;

begin
	counter: process(reset,clk,shift_start)
	begin
		if(reset = '0') then
			cnt <= (others => '0');
		elsif(clk'event and clk = '1') then
			if(shift_start = '0') then
				cnt <= cnt + 1;
			else
				cnt <= (others => '0');
			end if;
		end if;
	end process counter;
 
	fsm: block
	begin
		sync: process(reset,clk)
		begin
			if(reset= '0') then
				current_state <= idle;
			elsif(clk'event and clk = '1') then
				current_state <= next_state;
			end if;
		end process sync;

	comb: process(current_state,cnt,start)
	begin
		case current_state is
		when idle =>
			ready <= '0';
			reg_en <= '1';
			shift_start <= '1';
			data_valid <= '1';
		if(start = '0') then
			reg_en <= '0';
			next_state <= recieve;
		else
			next_state <= idle;
		end if;
		when recieve =>
			reg_en <= '1';
			ready <= '1';
			data_valid <= '0';
			shift_start <= '0';
			next_state <= shift;
		when shift =>
			reg_en <= '1';
			ready <= '1';
			data_valid <= '0';
		if(cnt = 16) then
			shift_start <= '1';
			next_state <= finish;
		else
			shift_start <= '0';      
			next_state <= shift;
		end if;
		when finish =>
			reg_en <= '1';
			ready <= '0';
			data_valid <= '1';
			shift_start <= '1';
			next_state <= idle;
		when others =>
			next_state <= idle;
	end case;
	end process comb;

	end block fsm;
 
 data_channel: process(reset,clk)
 begin
  if(reset = '0') then
   reg <= (others => '0');
   q   <= '0';
  elsif(clk'event and clk = '1') then
   if(reg_en = '0') then
    reg <= data_in;
   elsif(shift_start = '0') then
    q <= reg(15);
    for i in 15 downto 1 loop    --shift register
     reg(i) <= reg(i - 1);
    end loop;
    reg(0) <= '0';
   else  
    q <= '0';
   end if;
  end if;
 end process data_channel; 


end Behavioral;







并串轉換（16--1）

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity p2s16_1 is
    Port ( reset : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           start : in  STD_LOGIC;
           data_in : in  STD_LOGIC_VECTOR (15 downto 0);
           data_valid : out  STD_LOGIC;
           ready : out  STD_LOGIC;
           q : out  STD_LOGIC);
end p2s16_1;

architecture Behavioral of p2s16_1 is
signal reg : std_logic_vector(15 downto 0);
signal cnt : std_logic_vector(4 downto 0);
signal reg_en : std_logic;
signal shift_start : std_logic;
type state is (idle,recieve,shift,finish);
signal current_state, next_state : state;

begin
	counter: process(reset,clk,shift_start)
	begin
		if(reset = '0') then
			cnt <= (others => '0');
		elsif(clk'event and clk = '1') then
			if(shift_start = '0') then
				cnt <= cnt + 1;
			else
				cnt <= (others => '0');
			end if;
		end if;
	end process counter;
 
	fsm: block
	begin
		sync: process(reset,clk)
		begin
			if(reset= '0') then
				current_state <= idle;
			elsif(clk'event and clk = '1') then
				current_state <= next_state;
			end if;
		end process sync;

	comb: process(current_state,cnt,start)
	begin
		case current_state is
		when idle =>
			ready <= '0';
			reg_en <= '1';
			shift_start <= '1';
			data_valid <= '1';
		if(start = '0') then
			reg_en <= '0';
			next_state <= recieve;
		else
			next_state <= idle;
		end if;
		when recieve =>
			reg_en <= '1';
			ready <= '1';
			data_valid <= '0';
			shift_start <= '0';
			next_state <= shift;
		when shift =>
			reg_en <= '1';
			ready <= '1';
			data_valid <= '0';
		if(cnt = 16) then
			shift_start <= '1';
			next_state <= finish;
		else
			shift_start <= '0';      
			next_state <= shift;
		end if;
		when finish =>
			reg_en <= '1';
			ready <= '0';
			data_valid <= '1';
			shift_start <= '1';
			next_state <= idle;
		when others =>
			next_state <= idle;
	end case;
	end process comb;

	end block fsm;
 
 data_channel: process(reset,clk)
 begin
  if(reset = '0') then
   reg <= (others => '0');
   q   <= '0';
  elsif(clk'event and clk = '1') then
   if(reg_en = '0') then
    reg <= data_in;
   elsif(shift_start = '0') then
    q <= reg(15);
    for i in 15 downto 1 loop    --shift register
     reg(i) <= reg(i - 1);
    end loop;
    reg(0) <= '0';
   else  
    q <= '0';
   end if;
  end if;
 end process data_channel; 


end Behavioral;