Library IEEE;
Use IEEE.Std_logic_1164.all;
USe IEEE.Std_logic_unsigned.all;

ENTITY sram IS
	GENERIC
	(
		k: integer:=8;  --8位數據寬度
		w: integer:=4   --4位寬度地址，共16個地址
	);
	PORT
	(
		rd,wr,cs: IN STD_LOGIC;  --定義寫，讀，片選控制信號
		adr: IN	STD_LOGIC_VECTOR(w-1 DOWNTO 0); --4位地址信號
	    din: IN	STD_LOGIC_VECTOR(k-1 DOWNTO 0); --8位輸入信號
		dout: OUT STD_LOGIC_VECTOR(k-1 DOWNTO 0) --8位輸出信號
	);
END sram ;

ARCHITECTURE behave OF sram IS
	 subtype word is STD_LOGIC_VECTOR(k-1 DOWNTO 0);  
	 type memory is array(0 to 2**w-1) of word;
	  signal sram:memory; --定義中間緩存空間
	  signal adr_in:Integer;   --定義地址指向標志
BEGIN 
	 adr_in<=conv_integer(adr);	 --將輸入地址轉換為地址指向標志
Write:  process(wr,cs,adr_in,din,rd) --數據寫入進程：Write
          begin
          if wr='0' then
           	 if cs='0' and rd='1' then
              sram(adr_in)<=din;
             end if;
          end if;
         end process;
Read:   process(rd,cs,adr_in,wr)  --數據讀入進程:Read
          begin
           if(rd='0' and cs='0' and wr='1') then
            dout<=sram(adr_in);
           else dout<=(others=>'Z');
            end if;
         end process;
end behave;