--A1L361Q is vga_hs_control~reg0 at LC_X10_Y8_N9
--operation mode is normal

A1L361Q_lut_out = vga_h_sync;
A1L361Q = DFFEA(A1L361Q_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , , , );


--A1L071Q is vga_vs_control~reg0 at LC_X10_Y8_N6
--operation mode is normal

A1L071Q_lut_out = vga_v_sync;
A1L071Q = DFFEA(A1L071Q_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , , , );


--A1L661Q is vga_read_dispaly~reg0 at LC_X10_Y8_N7
--operation mode is normal

A1L661Q_lut_out = vga_h_sync & vga_read & vga_v_sync;
A1L661Q = DFFEA(A1L661Q_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , , , );


--A1L951Q is vga_green_dispaly~reg0 at LC_X10_Y8_N4
--operation mode is normal

A1L951Q_lut_out = vga_h_sync & vga_green & vga_v_sync;
A1L951Q = DFFEA(A1L951Q_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , , , );


--A1L251Q is vga_blue_dispaly~reg0 at LC_X10_Y8_N2
--operation mode is normal

A1L251Q_lut_out = vga_blue & vga_h_sync & vga_v_sync;
A1L251Q = DFFEA(A1L251Q_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , , , );


--vga_h_sync is vga_h_sync at LC_X10_Y8_N5
--operation mode is normal

vga_h_sync_lut_out = !count_x[7] & !count_x[8] # !count_x[9];
vga_h_sync = DFFEA(vga_h_sync_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , , , );


--clock_25mhz is clock_25mhz at LC_X11_Y6_N2
--operation mode is normal

clock_25mhz_lut_out = !clock_25mhz;
clock_25mhz = DFFEA(clock_25mhz_lut_out, GLOBAL(clock0), GLOBAL(reset), , , , );


--vga_v_sync is vga_v_sync at LC_X10_Y8_N3
--operation mode is normal

vga_v_sync_lut_out = !A1L541;
vga_v_sync = DFFEA(vga_v_sync_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , , , );


--vga_read is vga_read at LC_X15_Y6_N6
--operation mode is normal

vga_read_lut_out = !A1L631 & A1L061 & (count_z[4] # !A1L831);
vga_read = DFFEA(vga_read_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , A1L761, , );


--vga_green is vga_green at LC_X15_Y6_N8
--operation mode is normal

vga_green_lut_out = A1L061 & (A1L341 # count_z[4] # !count_z[3]);
vga_green = DFFEA(vga_green_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , A1L761, , );


--vga_blue is vga_blue at LC_X15_Y6_N1
--operation mode is normal

vga_blue_lut_out = A1L3 & E1L2 & (A1L651 # A1L451);
vga_blue = DFFEA(vga_blue_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , A1L761, , );


--count_x[8] is count_x[8] at LC_X11_Y7_N3
--operation mode is normal

count_x[8]_lut_out = A1L05 & !A1L841;
count_x[8] = DFFEA(count_x[8]_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , , , );


--count_x[9] is count_x[9] at LC_X10_Y8_N8
--operation mode is normal

count_x[9]_lut_out = !A1L841 & A1L45;
count_x[9] = DFFEA(count_x[9]_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , , , );


--count_y[8] is count_y[8] at LC_X11_Y7_N2
--operation mode is normal

count_y[8]_lut_out = A1L78 & (!A1L541 # !count_y[1] # !A1L041);
count_y[8] = DFFEA(count_y[8]_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , A1L841, , );


--count_y[7] is count_y[7] at LC_X10_Y7_N9
--operation mode is normal

count_y[7]_lut_out = A1L38 & (!A1L541 # !A1L041 # !count_y[1]);
count_y[7] = DFFEA(count_y[7]_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , A1L841, , );


--count_y[6] is count_y[6] at LC_X10_Y7_N3
--operation mode is normal

count_y[6]_lut_out = A1L97 & (!A1L541 # !A1L041 # !count_y[1]);
count_y[6] = DFFEA(count_y[6]_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , A1L841, , );


--count_y[5] is count_y[5] at LC_X10_Y7_N1
--operation mode is normal

count_y[5]_lut_out = A1L57 & (!A1L541 # !A1L041 # !count_y[1]);
count_y[5] = DFFEA(count_y[5]_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , A1L841, , );


--A1L541 is reduce_nor~108 at LC_X10_Y7_N8
--operation mode is normal

A1L541 = count_y[8] & count_y[6] & count_y[7] & count_y[5];


--D1_ram_block1a1 is tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ram_block1a1 at M4K_X13_Y8
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 1
--Port A Input: Registered, Port A Output: Un-registered
D1_ram_block1a1_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7], address[8], address[9], address[10], address[11]);
D1_ram_block1a1_PORT_A_address_reg = DFFE(D1_ram_block1a1_PORT_A_address, D1_ram_block1a1_clock_0, , , );
D1_ram_block1a1_clock_0 = GLOBAL(clock0);
D1_ram_block1a1_PORT_A_data_out = MEMORY(, , D1_ram_block1a1_PORT_A_address_reg, , , , , , D1_ram_block1a1_clock_0, , , , , );
D1_ram_block1a1 = D1_ram_block1a1_PORT_A_data_out[0];


--D1_ram_block1a2 is tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ram_block1a2 at M4K_X13_Y7
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 1
--Port A Input: Registered, Port A Output: Un-registered
D1_ram_block1a2_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7], address[8], address[9], address[10], address[11]);
D1_ram_block1a2_PORT_A_address_reg = DFFE(D1_ram_block1a2_PORT_A_address, D1_ram_block1a2_clock_0, , , );
D1_ram_block1a2_clock_0 = GLOBAL(clock0);
D1_ram_block1a2_PORT_A_data_out = MEMORY(, , D1_ram_block1a2_PORT_A_address_reg, , , , , , D1_ram_block1a2_clock_0, , , , , );
D1_ram_block1a2 = D1_ram_block1a2_PORT_A_data_out[0];


--D1_ram_block1a0 is tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ram_block1a0 at M4K_X13_Y5
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 1
--Port A Input: Registered, Port A Output: Un-registered
D1_ram_block1a0_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7], address[8], address[9], address[10], address[11]);
D1_ram_block1a0_PORT_A_address_reg = DFFE(D1_ram_block1a0_PORT_A_address, D1_ram_block1a0_clock_0, , , );
D1_ram_block1a0_clock_0 = GLOBAL(clock0);
D1_ram_block1a0_PORT_A_data_out = MEMORY(, , D1_ram_block1a0_PORT_A_address_reg, , , , , , D1_ram_block1a0_clock_0, , , , , );
D1_ram_block1a0 = D1_ram_block1a0_PORT_A_data_out[0];


--E1L1 is tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|mux_rab:mux2|w_result37w~37 at LC_X15_Y6_N3
--operation mode is normal

D1_address_reg_a[1]_qfbk = D1_address_reg_a[1];
E1L1 = D1_address_reg_a[1]_qfbk & (D1_address_reg_a[0] # D1_ram_block1a2) # !D1_address_reg_a[1]_qfbk & D1_ram_block1a0 & !D1_address_reg_a[0];

--D1_address_reg_a[1] is tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|address_reg_a[1] at LC_X15_Y6_N3
--operation mode is normal

D1_address_reg_a[1]_sload_eqn = address[13];
D1_address_reg_a[1] = DFFEA(D1_address_reg_a[1]_sload_eqn, GLOBAL(clock0), VCC, , , , );


--D1_ram_block1a3 is tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ram_block1a3 at M4K_X13_Y6
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 1
--Port A Input: Registered, Port A Output: Un-registered
D1_ram_block1a3_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7], address[8], address[9], address[10], address[11]);
D1_ram_block1a3_PORT_A_address_reg = DFFE(D1_ram_block1a3_PORT_A_address, D1_ram_block1a3_clock_0, , , );
D1_ram_block1a3_clock_0 = GLOBAL(clock0);
D1_ram_block1a3_PORT_A_data_out = MEMORY(, , D1_ram_block1a3_PORT_A_address_reg, , , , , , D1_ram_block1a3_clock_0, , , , , );
D1_ram_block1a3 = D1_ram_block1a3_PORT_A_data_out[0];


--E1L2 is tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|mux_rab:mux2|w_result37w~38 at LC_X15_Y6_N4
--operation mode is normal

D1_address_reg_a[0]_qfbk = D1_address_reg_a[0];
E1L2 = E1L1 & (D1_ram_block1a3 # !D1_address_reg_a[0]_qfbk) # !E1L1 & D1_ram_block1a1 & D1_address_reg_a[0]_qfbk;

--D1_address_reg_a[0] is tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|address_reg_a[0] at LC_X15_Y6_N4
--operation mode is normal

D1_address_reg_a[0]_sload_eqn = address[12];
D1_address_reg_a[0] = DFFEA(D1_address_reg_a[0]_sload_eqn, GLOBAL(clock0), VCC, , , , );


--A1L3 is address[0]~148 at LC_X11_Y7_N1
--operation mode is normal

A1L3 = !count_x[9] & (!count_x[6] # !count_x[8] # !count_x[7]);


--count_z[2] is count_z[2] at LC_X16_Y6_N8
--operation mode is normal

count_z[2]_lut_out = A1L69 & (count_z[1] # !A1L441 # !count_z[4]);
count_z[2] = DFFEA(count_z[2]_lut_out, GLOBAL(clock2), GLOBAL(reset), , , , );


--count_z[4] is count_z[4] at LC_X16_Y6_N5
--operation mode is normal

count_z[4]_lut_out = A1L401 & (count_z[1] # !count_z[4] # !A1L441);
count_z[4] = DFFEA(count_z[4]_lut_out, GLOBAL(clock2), GLOBAL(reset), , , , );


--count_z[1] is count_z[1] at LC_X16_Y6_N7
--operation mode is normal

count_z[1]_lut_out = A1L29 & (count_z[1] # !A1L441 # !count_z[4]);
count_z[1] = DFFEA(count_z[1]_lut_out, GLOBAL(clock2), GLOBAL(reset), , , , );


--A1L731 is process10~310 at LC_X16_Y6_N9
--operation mode is normal

count_z[3]_qfbk = count_z[3];
A1L731 = count_z[3]_qfbk # count_z[4] # !count_z[1] & !count_z[0];

--count_z[3] is count_z[3] at LC_X16_Y6_N9
--operation mode is normal

count_z[3]_sload_eqn = A1L001;
count_z[3] = DFFEA(count_z[3]_sload_eqn, GLOBAL(clock2), GLOBAL(reset), , , , );


--A1L061 is vga_green~124 at LC_X15_Y6_N5
--operation mode is normal

A1L061 = A1L3 & E1L2 & (count_z[2] # A1L731);


--A1L831 is process10~311 at LC_X15_Y5_N2
--operation mode is normal

A1L831 = count_z[1] & count_z[0] & !count_z[3] & count_z[2] # !count_z[1] & count_z[3] & !count_z[2];


--A1L931 is process10~312 at LC_X15_Y5_N7
--operation mode is normal

A1L931 = !count_z[3] & !count_z[4];


--A1L631 is process10~94 at LC_X15_Y5_N8
--operation mode is normal

A1L631 = count_z[2] & A1L931 & (!count_z[1] # !count_z[0]);


--count_y[3] is count_y[3] at LC_X15_Y7_N9
--operation mode is normal

count_y[3]_sload_eqn = A1L76;
count_y[3] = DFFEA(count_y[3]_sload_eqn, GLOBAL(clock_25mhz), GLOBAL(reset), , A1L841, , );


--count_y[2] is count_y[2] at LC_X12_Y6_N3
--operation mode is normal

count_y[2]_sload_eqn = A1L36;
count_y[2] = DFFEA(count_y[2]_sload_eqn, GLOBAL(clock_25mhz), GLOBAL(reset), , A1L841, , );


--count_y[0] is count_y[0] at LC_X15_Y7_N3
--operation mode is normal

count_y[0]_lut_out = A1L55 & (!A1L541 # !A1L041 # !count_y[1]);
count_y[0] = DFFEA(count_y[0]_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , A1L841, , );


--A1L041 is process10~313 at LC_X11_Y7_N9
--operation mode is normal

count_y[4]_qfbk = count_y[4];
A1L041 = !count_y[2] & !count_y[3] & !count_y[4]_qfbk & !count_y[0];

--count_y[4] is count_y[4] at LC_X11_Y7_N9
--operation mode is normal

count_y[4]_sload_eqn = A1L17;
count_y[4] = DFFEA(count_y[4]_sload_eqn, GLOBAL(clock_25mhz), GLOBAL(reset), , A1L841, , );


--count_y[1] is count_y[1] at LC_X10_Y7_N2
--operation mode is normal

count_y[1]_lut_out = A1L95 & (!A1L541 # !A1L041 # !count_y[1]);
count_y[1] = DFFEA(count_y[1]_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , A1L841, , );


--A1L141 is process10~314 at LC_X11_Y7_N5
--operation mode is normal

A1L141 = !count_y[8] & !count_y[1] & !count_y[6] & !count_y[5];


--A1L241 is process10~315 at LC_X11_Y7_N6
--operation mode is normal

A1L241 = A1L041 & (A1L141 # count_y[8] $ !count_y[7]) # !A1L041 & (count_y[8] $ !count_y[7]);


--A1L761 is vga_read~4 at LC_X15_Y6_N2
--operation mode is normal

A1L761 = !count_x[9] & !A1L241;


--A1L341 is process10~316 at LC_X15_Y5_N6
--operation mode is normal

A1L341 = !count_z[1] & !count_z[2];


--A1L351 is vga_blue~497 at LC_X15_Y6_N9
--operation mode is normal

A1L351 = count_z[1] & count_z[2] # !count_z[1] & (count_z[0] # !count_z[2]) # !count_z[3];


--A1L451 is vga_blue~498 at LC_X15_Y6_N0
--operation mode is normal

A1L451 = A1L351 & !A1L631 & !count_z[4];


--A1L551 is vga_blue~499 at LC_X15_Y5_N5
--operation mode is normal

A1L551 = count_z[3] # count_z[2] # count_z[0] & count_z[1];


--A1L651 is vga_blue~500 at LC_X15_Y6_N7
--operation mode is normal

A1L651 = count_z[2] & count_z[4] & A1L551 # !count_z[2] & (count_z[4] & A1L551 # !A1L731);


--A1L05 is add~34 at LC_X11_Y8_N8
--operation mode is arithmetic

A1L05_carry_eqn = (!A1L73 & A1L84) # (A1L73 & A1L94);
A1L05 = count_x[8] $ !A1L05_carry_eqn;

--A1L25 is add~34COUT0 at LC_X11_Y8_N8
--operation mode is arithmetic

A1L25_cout_0 = count_x[8] & !A1L84;
A1L25 = CARRY(A1L25_cout_0);

--A1L35 is add~34COUT1 at LC_X11_Y8_N8
--operation mode is arithmetic

A1L35_cout_1 = count_x[8] & !A1L94;
A1L35 = CARRY(A1L35_cout_1);


--A1L641 is reduce_nor~109 at LC_X11_Y7_N4
--operation mode is normal

count_x[6]_qfbk = count_x[6];
A1L641 = count_x[7] # count_x[6]_qfbk # !count_x[9] # !count_x[8];

--count_x[6] is count_x[6] at LC_X11_Y7_N4
--operation mode is normal

count_x[6]_sload_eqn = A1L24;
count_x[6] = DFFEA(count_x[6]_sload_eqn, GLOBAL(clock_25mhz), GLOBAL(reset), , , , );


--count_x[5] is count_x[5] at LC_X10_Y7_N0
--operation mode is normal

count_x[5]_lut_out = !A1L841 & A1L83;
count_x[5] = DFFEA(count_x[5]_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , , , );


--count_x[2] is count_x[2] at LC_X10_Y7_N4
--operation mode is normal

count_x[2]_lut_out = A1L82;
count_x[2] = DFFEA(count_x[2]_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , , , );


--A1L741 is reduce_nor~110 at LC_X10_Y7_N5
--operation mode is normal

count_x[3]_qfbk = count_x[3];
A1L741 = count_x[5] # !count_x[3]_qfbk # !count_x[2] # !count_x[4];

--count_x[3] is count_x[3] at LC_X10_Y7_N5
--operation mode is normal

count_x[3]_sload_eqn = A1L23;
count_x[3] = DFFEA(count_x[3]_sload_eqn, GLOBAL(clock_25mhz), GLOBAL(reset), , , , );


--A1L841 is reduce_nor~111 at LC_X10_Y7_N6
--operation mode is normal

count_x[0]_qfbk = count_x[0];
A1L841 = count_x[1] & !A1L641 & count_x[0]_qfbk & !A1L741;

--count_x[0] is count_x[0] at LC_X10_Y7_N6
--operation mode is normal

count_x[0]_sload_eqn = A1L02;
count_x[0] = DFFEA(count_x[0]_sload_eqn, GLOBAL(clock_25mhz), GLOBAL(reset), , , , );


--A1L64 is add~33 at LC_X11_Y8_N7
--operation mode is arithmetic

A1L64_carry_eqn = (!A1L73 & A1L44) # (A1L73 & A1L54);
A1L64 = count_x[7] $ A1L64_carry_eqn;

--A1L84 is add~33COUT0 at LC_X11_Y8_N7
--operation mode is arithmetic

A1L84_cout_0 = !A1L44 # !count_x[7];
A1L84 = CARRY(A1L84_cout_0);

--A1L94 is add~33COUT1 at LC_X11_Y8_N7
--operation mode is arithmetic

A1L94_cout_1 = !A1L54 # !count_x[7];
A1L94 = CARRY(A1L94_cout_1);


--A1L45 is add~35 at LC_X11_Y8_N9
--operation mode is normal

A1L45_carry_eqn = (!A1L73 & A1L25) # (A1L73 & A1L35);
A1L45 = count_x[9] $ A1L45_carry_eqn;


--A1L78 is add~44 at LC_X12_Y7_N8
--operation mode is normal

A1L78_carry_eqn = (!A1L27 & A1L58) # (A1L27 & A1L68);
A1L78 = A1L78_carry_eqn $ !count_y[8];


--A1L38 is add~43 at LC_X12_Y7_N7
--operation mode is arithmetic

A1L38_carry_eqn = (!A1L27 & A1L18) # (A1L27 & A1L28);
A1L38 = count_y[7] $ A1L38_carry_eqn;

--A1L58 is add~43COUT0 at LC_X12_Y7_N7
--operation mode is arithmetic

A1L58_cout_0 = !A1L18 # !count_y[7];
A1L58 = CARRY(A1L58_cout_0);

--A1L68 is add~43COUT1 at LC_X12_Y7_N7
--operation mode is arithmetic

A1L68_cout_1 = !A1L28 # !count_y[7];
A1L68 = CARRY(A1L68_cout_1);


--A1L97 is add~42 at LC_X12_Y7_N6
--operation mode is arithmetic

A1L97_carry_eqn = (!A1L27 & A1L77) # (A1L27 & A1L87);
A1L97 = count_y[6] $ !A1L97_carry_eqn;

--A1L18 is add~42COUT0 at LC_X12_Y7_N6
--operation mode is arithmetic

A1L18_cout_0 = count_y[6] & !A1L77;
A1L18 = CARRY(A1L18_cout_0);

--A1L28 is add~42COUT1 at LC_X12_Y7_N6
--operation mode is arithmetic

A1L28_cout_1 = count_y[6] & !A1L87;
A1L28 = CARRY(A1L28_cout_1);


--A1L57 is add~41 at LC_X12_Y7_N5
--operation mode is arithmetic

A1L57_carry_eqn = (!A1L27 & GND) # (A1L27 & VCC);
A1L57 = count_y[5] $ A1L57_carry_eqn;

--A1L77 is add~41COUT0 at LC_X12_Y7_N5