Version 4.1 Build 181 06/29/2004 SJ Full Version
31
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# entity
cntr_vu7
# case_insensitive
# source_file
db|cntr_vu7.tdf
1114328786
6
# storage
db|vgainterface.(2).cnf
db|vgainterface.(2).cnf
# used_port {
clock
clk_en
aclr
q0
q1
q2
q3
q4
q5
q6
q7
q8
}
# end
# entity
altsyncram_fiq
# case_insensitive
# source_file
db|altsyncram_fiq.tdf
1114391042
6
# storage
db|vgainterface.(7).cnf
db|vgainterface.(7).cnf
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
address_a10
address_a11
address_a12
address_a13
clock0
q_a0
}
# memory_file {
code.hex
1114388104
}
# end
# entity
mux_rab
# case_insensitive
# source_file
db|mux_rab.tdf
1114391042
6
# storage
db|vgainterface.(8).cnf
db|vgainterface.(8).cnf
# used_port {
data0
data1
data2
data3
sel0
sel1
result0
}
# end
# entity
cntr_ea7
# case_insensitive
# source_file
db|cntr_ea7.tdf
1114406844
6
# storage
db|vgainterface.(14).cnf
db|vgainterface.(14).cnf
# used_port {
clock
aclr
q0
q1
q2
q3
}
# end
# entity
mux_gcb
# case_insensitive
# source_file
db|mux_gcb.tdf
1114501136
6
# storage
db|vgainterface.(12).cnf
db|vgainterface.(12).cnf
# used_port {
data0
data1
data2
data3
data4
data5
data6
data7
data8
data9
data10
data11
data12
data13
data14
data15
sel0
sel1
sel2
sel3
result0
}
# end
# entity
mux_2bb
# case_insensitive
# source_file
db|mux_2bb.tdf
1114502104
6
# storage
db|vgainterface.(17).cnf
db|vgainterface.(17).cnf
# used_port {
data0
data1
data2
data3
data4
data5
data6
data7
data8
sel0
sel1
sel2
sel3
result0
}
# end
# entity
vgainterface
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
vgainterface.vhd
1114504436
4
# storage
db|vgainterface.(0).cnf
db|vgainterface.(0).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
tsinghua
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
tsinghua.vhd
1114504288
4
# storage
db|vgainterface.(3).cnf
db|vgainterface.(3).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
altsyncram_qcr
# case_insensitive
# source_file
db|altsyncram_qcr.tdf
1114404076
6
# storage
db|vgainterface.(16).cnf
db|vgainterface.(16).cnf
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
address_a10
address_a11
address_a12
address_a13
clock0
q_a0
}
# memory_file {
vgainterface.mif
1114504250
}
# end
# entity
altsyncram
# case_insensitive
# source_file
d:|altera|quartus41|libraries|megafunctions|altsyncram.tdf
1088009418
6
# storage
db|vgainterface.(1).cnf
db|vgainterface.(1).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
1
PARAMETER_DEC
USR
WIDTHAD_A
14
PARAMETER_DEC
USR
NUMWORDS_A
16384
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
vgainterface.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_qcr
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a0
address_a10
address_a11
address_a12
address_a13
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
clock0
q_a0
}
# include_file {
d:|altera|quartus41|libraries|megafunctions|stratix_ram_block.inc
1081479498
d:|altera|quartus41|libraries|megafunctions|lpm_mux.inc
1081478758
d:|altera|quartus41|libraries|megafunctions|lpm_decode.inc
1081478592
d:|altera|quartus41|libraries|megafunctions|aglobal41.inc
1088009406
d:|altera|quartus41|libraries|megafunctions|altsyncram.inc
1081477654
d:|altera|quartus41|libraries|megafunctions|a_rdenreg.inc
1081476578
d:|altera|quartus41|libraries|megafunctions|altrom.inc
1081477590
d:|altera|quartus41|libraries|megafunctions|altram.inc
1081477560
d:|altera|quartus41|libraries|megafunctions|altdpram.inc
1081477328
d:|altera|quartus41|libraries|megafunctions|altqpram.inc
1081477546
}
# end
# complete