{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jul 05 12:38:44 2005 " "Info: Processing started: Tue Jul 05 12:38:44 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off vgainterface -c vgainterface " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off vgainterface -c vgainterface" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vgainterface.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file vgainterface.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 vgainterface-vgainterface " "Info: Found design unit 1: vgainterface-vgainterface" {  } { { "E:/VGA_example/VGA_example/VGA_test2/vgainterface/vgainterface.vhd" "vgainterface-vgainterface" "" { Text "E:/VGA_example/VGA_example/VGA_test2/vgainterface/vgainterface.vhd" 20 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 vgainterface " "Info: Found entity 1: vgainterface" {  } { { "E:/VGA_example/VGA_example/VGA_test2/vgainterface/vgainterface.vhd" "vgainterface" "" { Text "E:/VGA_example/VGA_example/VGA_test2/vgainterface/vgainterface.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "tsinghua.vhd 2 1 " "Info: Using design file tsinghua.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 tsinghua-SYN " "Info: Found design unit 1: tsinghua-SYN" {  } { { "E:/VGA_example/VGA_example/VGA_test2/vgainterface/tsinghua.vhd" "tsinghua-SYN" "" { Text "E:/VGA_example/VGA_example/VGA_test2/vgainterface/tsinghua.vhd" 55 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 tsinghua " "Info: Found entity 1: tsinghua" {  } { { "E:/VGA_example/VGA_example/VGA_test2/vgainterface/tsinghua.vhd" "tsinghua" "" { Text "E:/VGA_example/VGA_example/VGA_test2/vgainterface/tsinghua.vhd" 45 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus41/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "d:/altera/quartus41/libraries/megafunctions/altsyncram.tdf" "altsyncram" "" { Text "d:/altera/quartus41/libraries/megafunctions/altsyncram.tdf" 431 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_qcr.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_qcr.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_qcr " "Info: Found entity 1: altsyncram_qcr" {  } { { "E:/VGA_example/VGA_example/VGA_test2/vgainterface/db/altsyncram_qcr.tdf" "altsyncram_qcr" "" { Text "E:/VGA_example/VGA_example/VGA_test2/vgainterface/db/altsyncram_qcr.tdf" 33 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_rab.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_rab.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_rab " "Info: Found entity 1: mux_rab" {  } { { "E:/VGA_example/VGA_example/VGA_test2/vgainterface/db/mux_rab.tdf" "mux_rab" "" { Text "E:/VGA_example/VGA_example/VGA_test2/vgainterface/db/mux_rab.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "113 " "Info: Implemented 113 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "5 " "Info: Implemented 5 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "101 " "Info: Implemented 101 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_RAMS" "4 " "Info: Implemented 4 RAM segments" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jul 05 12:38:49 2005 " "Info: Processing ended: Tue Jul 05 12:38:49 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}