?? altsyncram_vcr.tdf
字號:
--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" ENABLE_RUNTIME_MOD="NO" INIT_FILE="vgainterface.mif" NUMWORDS_A=65536 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="UNREGISTERED" WIDTH_A=1 WIDTH_BYTEENA_A=1 WIDTHAD_A=16 address_a clock0 q_a
--VERSION_BEGIN 4.1 cbx_altsyncram 2004:06:23:18:19:30:SJ cbx_cycloneii 2004:05:18:11:27:16:SJ cbx_lpm_add_sub 2004:06:23:12:24:04:SJ cbx_lpm_compare 2004:04:12:17:30:12:SJ cbx_lpm_decode 2004:03:10:10:44:06:SJ cbx_lpm_mux 2004:03:10:10:50:34:SJ cbx_mgl 2004:06:17:17:30:06:SJ cbx_stratix 2004:04:28:15:20:14:SJ cbx_stratixii 2004:05:18:11:28:28:SJ cbx_util 2004:03:29:17:03:30:SJ VERSION_END
-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related netlist (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only
-- to program PLD devices (but not masked PLD devices) from Altera. Any
-- other use of such megafunction design, netlist, support information,
-- device programming or simulation file, or any other related documentation
-- or information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to the
-- intellectual property, including patents, copyrights, trademarks, trade
-- secrets, or maskworks, embodied in any such megafunction design, netlist,
-- support information, device programming or simulation file, or any other
-- related documentation or information provided by Altera or a megafunction
-- partner, remains with Altera, the megafunction partner, or their respective
-- licensors. No other licenses, including any licenses needed under any third
-- party's intellectual property, are provided herein.
FUNCTION mux_gcb (data[15..0], sel[3..0])
RETURNS ( result[0..0]);
FUNCTION cyclone_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, portaaddr[15..0], portabyteenamasks[15..0], portadatain[143..0], portawe, portbaddr[15..0], portbbyteenamasks[15..0], portbdatain[71..0], portbrewe)
WITH ( CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem1, mem2, mem3, mem4, mem5, mem6, mem7, mem8, mem9, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH, PORT_A_BYTE_ENABLE_CLEAR, PORT_A_BYTE_ENABLE_MASK_WIDTH, PORT_A_DATA_IN_CLEAR, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_WRITE_ENABLE_CLEAR, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH, PORT_B_BYTE_ENABLE_CLEAR, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH, PORT_B_DATA_IN_CLEAR, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE)
RETURNS ( portadataout[143..0], portbdataout[143..0]);
--synthesis_resources = lut 4 ram_bits (auto) 65536
SUBDESIGN altsyncram_vcr
(
address_a[15..0] : input;
clock0 : input;
q_a[0..0] : output;
)
VARIABLE
address_reg_a[3..0] : dffe;
mux2 : mux_gcb;
ram_block1a0 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "vgainterface.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 4095,
PORT_A_LOGICAL_RAM_DEPTH = 65536,
PORT_A_LOGICAL_RAM_WIDTH = 1,
RAM_BLOCK_TYPE = "auto"
);
ram_block1a1 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "vgainterface.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 65536,
PORT_A_LOGICAL_RAM_WIDTH = 1,
RAM_BLOCK_TYPE = "auto"
);
ram_block1a2 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "vgainterface.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 12287,
PORT_A_LOGICAL_RAM_DEPTH = 65536,
PORT_A_LOGICAL_RAM_WIDTH = 1,
RAM_BLOCK_TYPE = "auto"
);
ram_block1a3 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "vgainterface.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 12288,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 65536,
PORT_A_LOGICAL_RAM_WIDTH = 1,
RAM_BLOCK_TYPE = "auto"
);
ram_block1a4 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "vgainterface.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 16384,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 20479,
PORT_A_LOGICAL_RAM_DEPTH = 65536,
PORT_A_LOGICAL_RAM_WIDTH = 1,
RAM_BLOCK_TYPE = "auto"
);
ram_block1a5 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "vgainterface.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 20480,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 24575,
PORT_A_LOGICAL_RAM_DEPTH = 65536,
PORT_A_LOGICAL_RAM_WIDTH = 1,
RAM_BLOCK_TYPE = "auto"
);
ram_block1a6 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "vgainterface.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 24576,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 28671,
PORT_A_LOGICAL_RAM_DEPTH = 65536,
PORT_A_LOGICAL_RAM_WIDTH = 1,
RAM_BLOCK_TYPE = "auto"
);
ram_block1a7 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "vgainterface.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 28672,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 32767,
PORT_A_LOGICAL_RAM_DEPTH = 65536,
PORT_A_LOGICAL_RAM_WIDTH = 1,
RAM_BLOCK_TYPE = "auto"
);
ram_block1a8 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "vgainterface.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 32768,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 36863,
PORT_A_LOGICAL_RAM_DEPTH = 65536,
PORT_A_LOGICAL_RAM_WIDTH = 1,
RAM_BLOCK_TYPE = "auto"
);
ram_block1a9 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "vgainterface.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 36864,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 40959,
PORT_A_LOGICAL_RAM_DEPTH = 65536,
PORT_A_LOGICAL_RAM_WIDTH = 1,
RAM_BLOCK_TYPE = "auto"
);
ram_block1a10 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "vgainterface.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 40960,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 45055,
PORT_A_LOGICAL_RAM_DEPTH = 65536,
PORT_A_LOGICAL_RAM_WIDTH = 1,
RAM_BLOCK_TYPE = "auto"
);
ram_block1a11 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "vgainterface.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 45056,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 49151,
PORT_A_LOGICAL_RAM_DEPTH = 65536,
PORT_A_LOGICAL_RAM_WIDTH = 1,
RAM_BLOCK_TYPE = "auto"
);
ram_block1a12 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "vgainterface.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 49152,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 53247,
PORT_A_LOGICAL_RAM_DEPTH = 65536,
PORT_A_LOGICAL_RAM_WIDTH = 1,
RAM_BLOCK_TYPE = "auto"
);
ram_block1a13 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "vgainterface.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 53248,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 57343,
PORT_A_LOGICAL_RAM_DEPTH = 65536,
PORT_A_LOGICAL_RAM_WIDTH = 1,
RAM_BLOCK_TYPE = "auto"
);
ram_block1a14 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "vgainterface.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 57344,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 61439,
PORT_A_LOGICAL_RAM_DEPTH = 65536,
PORT_A_LOGICAL_RAM_WIDTH = 1,
RAM_BLOCK_TYPE = "auto"
);
ram_block1a15 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "vgainterface.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 61440,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 65535,
PORT_A_LOGICAL_RAM_DEPTH = 65536,
PORT_A_LOGICAL_RAM_WIDTH = 1,
RAM_BLOCK_TYPE = "auto"
);
clocken0 : NODE;
BEGIN
address_reg_a[].CLK = clock0;
address_reg_a[].D = address_a[15..12];
address_reg_a[].ENA = clocken0;
mux2.data[] = ( ram_block1a[15].portadataout[0..0], ram_block1a[14].portadataout[0..0], ram_block1a[13].portadataout[0..0], ram_block1a[12].portadataout[0..0], ram_block1a[11].portadataout[0..0], ram_block1a[10].portadataout[0..0], ram_block1a[9].portadataout[0..0], ram_block1a[8].portadataout[0..0], ram_block1a[7].portadataout[0..0], ram_block1a[6].portadataout[0..0], ram_block1a[5].portadataout[0..0], ram_block1a[4].portadataout[0..0], ram_block1a[3].portadataout[0..0], ram_block1a[2].portadataout[0..0], ram_block1a[1].portadataout[0..0], ram_block1a[0].portadataout[0..0]);
mux2.sel[] = address_reg_a[].Q;
ram_block1a[15..0].clk0 = clock0;
ram_block1a[0].portaaddr[] = ( B"0000", address_a[11..0]);
ram_block1a[1].portaaddr[] = ( B"0000", address_a[11..0]);
ram_block1a[2].portaaddr[] = ( B"0000", address_a[11..0]);
ram_block1a[3].portaaddr[] = ( B"0000", address_a[11..0]);
ram_block1a[4].portaaddr[] = ( B"0000", address_a[11..0]);
ram_block1a[5].portaaddr[] = ( B"0000", address_a[11..0]);
ram_block1a[6].portaaddr[] = ( B"0000", address_a[11..0]);
ram_block1a[7].portaaddr[] = ( B"0000", address_a[11..0]);
ram_block1a[8].portaaddr[] = ( B"0000", address_a[11..0]);
ram_block1a[9].portaaddr[] = ( B"0000", address_a[11..0]);
ram_block1a[10].portaaddr[] = ( B"0000", address_a[11..0]);
ram_block1a[11].portaaddr[] = ( B"0000", address_a[11..0]);
ram_block1a[12].portaaddr[] = ( B"0000", address_a[11..0]);
ram_block1a[13].portaaddr[] = ( B"0000", address_a[11..0]);
ram_block1a[14].portaaddr[] = ( B"0000", address_a[11..0]);
ram_block1a[15].portaaddr[] = ( B"0000", address_a[11..0]);
clocken0 = VCC;
q_a[] = mux2.result[];
END;
--VALID FILE
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