{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 26 12:19:41 2005 " "Info: Processing started: Tue Apr 26 12:19:41 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --import_settings_files=off --export_settings_files=off vgainterface -c vgainterface " "Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off vgainterface -c vgainterface" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "vgainterface EP1C3T144C6 " "Info: Selected device EP1C3T144C6 for design vgainterface" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation -- Fitter effort may be decreased to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6T144C6 " "Info: Device EP1C6T144C6 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "clock_25mhz Global clock " "Info: Automatically promoted some destinations of signal clock_25mhz to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clock_25mhz " "Info: Destination clock_25mhz may be non-global or may not use global clock" {  } { { "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" 67 -1 0 } }  } 0}  } { { "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" 67 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clock0 Global clock " "Info: Automatically promoted signal clock0 to use Global clock" {  } { { "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" 9 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "clock0 " "Info: Pin clock0 drives global clock, but is not placed in a dedicated clock pin position" {  } { { "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" 9 -1 0 } } { "c:/program files/eda/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/program files/eda/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clock0" } } } } { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { clock0 } "NODE_NAME" } } } { "F:/program_test/VGA_test1/vgainterface/vgainterface.fld" "" "" { Floorplan "F:/program_test/VGA_test1/vgainterface/vgainterface.fld" "" "" { clock0 } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clock2 Global clock " "Info: Automatically promoted signal clock2 to use Global clock" {  } { { "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" 10 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "clock2 " "Info: Pin clock2 drives global clock, but is not placed in a dedicated clock pin position" {  } { { "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" 10 -1 0 } } { "c:/program files/eda/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/program files/eda/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clock2" } } } } { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { clock2 } "NODE_NAME" } } } { "F:/program_test/VGA_test1/vgainterface/vgainterface.fld" "" "" { Floorplan "F:/program_test/VGA_test1/vgainterface/vgainterface.fld" "" "" { clock2 } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "reset Global clock " "Info: Automatically promoted signal reset to use Global clock" {  } { { "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" 8 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "reset " "Info: Pin reset drives global clock, but is not placed in a dedicated clock pin position" {  } { { "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" 8 -1 0 } } { "c:/program files/eda/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/program files/eda/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "reset" } } } } { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { reset } "NODE_NAME" } } } { "F:/program_test/VGA_test1/vgainterface/vgainterface.fld" "" "" { Floorplan "F:/program_test/VGA_test1/vgainterface/vgainterface.fld" "" "" { reset } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_START_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Start DSP scan-chain inferencing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Completed DSP scan-chain inferencing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_START_LUT_IO_MAC_RAM_PACKING" "" "Info: Moving registers into I/Os, LUTs, DSP and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFYGR_FYGR_FINISH_LUT_IO_MAC_RAM_PACKING" "" "Info: Finished moving registers into I/Os, LUTs, DSP and RAM blocks" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "0 " "Info: Fitter placement preparation operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "1.493 ns register memory " "Info: Estimated most critical path is register to memory delay of 1.493 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns address\[0\] 1 REG LAB_X15_Y12 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X15_Y12; Fanout = 4; REG Node = 'address\[0\]'" {  } { { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { address[0] } "NODE_NAME" } } } { "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" 215 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.198 ns) + CELL(0.295 ns) 1.493 ns tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|ram_block1a2~porta_address_reg0 2 MEM M4K_X13_Y13 1 " "Info: 2: + IC(1.198 ns) + CELL(0.295 ns) = 1.493 ns; Loc. = M4K_X13_Y13; Fanout = 1; MEM Node = 'tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|ram_block1a2~porta_address_reg0'" {  } { { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "1.493 ns" { address[0] tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ram_block1a2~porta_address_reg0 } "NODE_NAME" } } } { "F:/program_test/VGA_test1/vgainterface/db/altsyncram_qcr.tdf" "" "" { Text "F:/program_test/VGA_test1/vgainterface/db/altsyncram_qcr.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.295 ns 19.76 % " "Info: Total cell delay = 0.295 ns ( 19.76 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.198 ns 80.24 % " "Info: Total interconnect delay = 1.198 ns ( 80.24 % )" {  } {  } 0}  } { { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "1.493 ns" { address[0] tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ram_block1a2~porta_address_reg0 } "NODE_NAME" } } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PLACER_ESTIMATED_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Info: Estimated interconnect usage is 1% of the available device resources" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "0 " "Info: Fitter placement operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "0 " "Info: Fitter routing operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 26 12:19:47 2005 " "Info: Processing ended: Tue Apr 26 12:19:47 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0}  } {  } 0}