?? uart_tx_tb.vhd

?? URAT異步通信接口的VHDL描述
?? VHD
?? 第 1 頁 / 共 5 頁
字號:

    -- Write 2nd data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"10101010",CS,ADSn,WRn,A,DIN);

    -- Write 3rd data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"01011010",CS,ADSn,WRn,A,DIN);

    -- Write 4th data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"10100101",CS,ADSn,WRn,A,DIN);


    wait until falling_edge(PCLK);
    -- Test 3 ----------------------------------------------------
    --   5-bit data, odd parity, 1 stop
    TestID <= 3;

    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        -- Read LSR (check if "TEMT" flag at bit 6 is set)
        read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
        exit when regData_readBack(6) = '1';
        i := i + 1;
      else
        assert (false) report"Data Transmission Failed"
        severity failure;
      end if;
    end loop;
    wait for (16*CLK_PERIOD);

    -- LCR Intialization
    --   bit 6 : 0, do not set break
    --   bit 5 : 0, not stick parity
    --   bit 4 : 0, odd parity selected
    --   bit 3 : 1, parity enabled
    --   bit 2 : 0, 1 stop bit
    --   bit 1 : 0, 5 data bit (bit[1-0]="00")
    --   bit 0 : 0, 5 data bit (bit[1-0]="00")
    write_reg (LCR,"00001000",CS,ADSn,WRn,A,DIN);

    -- Write 1st data to THR
    write_reg (THR,"01010101",CS,ADSn,WRn,A,DIN);

    -- Write 2nd data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"10101010",CS,ADSn,WRn,A,DIN);

    -- Write 3rd data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"01011010",CS,ADSn,WRn,A,DIN);

    -- Write 4th data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"10100101",CS,ADSn,WRn,A,DIN);


    wait until falling_edge(PCLK);
    -- Test 4 ----------------------------------------------------
    --   5-bit data, odd parity, 1.5 stop
    TestID <= 4;

    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        -- Read LSR (check if "TEMT" flag at bit 6 is set)
        read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
        exit when regData_readBack(6) = '1';
        i := i + 1;
      else
        assert (false) report"Data Transmission Failed"
        severity failure;
      end if;
    end loop;
    wait for (16*CLK_PERIOD);

    -- LCR Intialization
    --   bit 6 : 0, do not set break
    --   bit 5 : 0, not stick parity
    --   bit 4 : 0, odd parity selected
    --   bit 3 : 1, parity enabled
    --   bit 2 : 1, 1.5 stop bit
    --   bit 1 : 0, 5 data bit (bit[1-0]="00")
    --   bit 0 : 0, 5 data bit (bit[1-0]="00")
    write_reg (LCR,"00001100",CS,ADSn,WRn,A,DIN);

    -- Write 1st data to THR
    write_reg (THR,"01010101",CS,ADSn,WRn,A,DIN);

    -- Write 2nd data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"10101010",CS,ADSn,WRn,A,DIN);

    -- Write 3rd data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"01011010",CS,ADSn,WRn,A,DIN);

    -- Write 4th data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"10100101",CS,ADSn,WRn,A,DIN);


    wait until falling_edge(PCLK);
    -- Test 5 ----------------------------------------------------
    --   5-bit data, stick even parity, 1 stop
    TestID <= 5;

    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        -- Read LSR (check if "TEMT" flag at bit 6 is set)
        read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
        exit when regData_readBack(6) = '1';
        i := i + 1;
      else
        assert (false) report"Data Transmission Failed"
        severity failure;
      end if;
    end loop;
    wait for (16*CLK_PERIOD);

    -- LCR Intialization
    --   bit 6 : 0, do not set break
    --   bit 5 : 1, stick parity
    --   bit 4 : 1, even parity selected
    --   bit 3 : 1, parity enabled
    --   bit 2 : 0, 1 stop bit
    --   bit 1 : 0, 5 data bit (bit[1-0]="00")
    --   bit 0 : 0, 5 data bit (bit[1-0]="00")
    write_reg (LCR,"00111000",CS,ADSn,WRn,A,DIN);

    -- Write 1st data to THR
    write_reg (THR,"01010101",CS,ADSn,WRn,A,DIN);

    -- Write 2nd data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"10101010",CS,ADSn,WRn,A,DIN);

    -- Write 3rd data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"01011010",CS,ADSn,WRn,A,DIN);

    -- Write 4th data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"10100101",CS,ADSn,WRn,A,DIN);


    wait until falling_edge(PCLK);
    -- Test 6 ----------------------------------------------------
    --   5-bit data, stick even parity, 1.5 stop
    TestID <= 6;

    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        -- Read LSR (check if "TEMT" flag at bit 6 is set)
        read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
        exit when regData_readBack(6) = '1';
        i := i + 1;
      else
        assert (false) report"Data Transmission Failed"
        severity failure;
      end if;
    end loop;
    wait for (16*CLK_PERIOD);

    -- LCR Intialization
    --   bit 6 : 0, do not set break
    --   bit 5 : 1, stick parity
    --   bit 4 : 1, even parity selected
    --   bit 3 : 1, parity enabled
    --   bit 2 : 1, 1.5 stop bit
    --   bit 1 : 0, 5 data bit (bit[1-0]="00")
    --   bit 0 : 0, 5 data bit (bit[1-0]="00")
    write_reg (LCR,"00111100",CS,ADSn,WRn,A,DIN);

    -- Write 1st data to THR
    write_reg (THR,"01010101",CS,ADSn,WRn,A,DIN);

    -- Write 2nd data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"10101010",CS,ADSn,WRn,A,DIN);

    -- Write 3rd data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"01011010",CS,ADSn,WRn,A,DIN);

    -- Write 4th data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"10100101",CS,ADSn,WRn,A,DIN);


    wait until falling_edge(PCLK);
    -- Test 7 ----------------------------------------------------
    --   5-bit data, stick odd parity, 1 stop
    TestID <= 7;

    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        -- Read LSR (check if "TEMT" flag at bit 6 is set)
        read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
        exit when regData_readBack(6) = '1';
        i := i + 1;
      else
        assert (false) report"Data Transmission Failed"
        severity failure;
      end if;
    end loop;
    wait for (16*CLK_PERIOD);

    -- LCR Intialization
    --   bit 6 : 0, do not set break
    --   bit 5 : 1, stick parity
    --   bit 4 : 0, odd parity selected
    --   bit 3 : 1, parity enabled
    --   bit 2 : 0, 1 stop bit
    --   bit 1 : 0, 5 data bit (bit[1-0]="00")
    --   bit 0 : 0, 5 data bit (bit[1-0]="00")
    write_reg (LCR,"00101000",CS,ADSn,WRn,A,DIN);

    -- Write 1st data to THR
    write_reg (THR,"01010101",CS,ADSn,WRn,A,DIN);

    -- Write 2nd data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"10101010",CS,ADSn,WRn,A,DIN);

    -- Write 3rd data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"01011010",CS,ADSn,WRn,A,DIN);

    -- Write 4th data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"10100101",CS,ADSn,WRn,A,DIN);


    wait until falling_edge(PCLK);
    -- Test 8 ----------------------------------------------------
    --   5-bit data, stick odd parity, 1.5 stop
    TestID <= 8;

    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        -- Read LSR (check if "TEMT" flag at bit 6 is set)
        read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
        exit when regData_readBack(6) = '1';
        i := i + 1;
      else
        assert (false) report"Data Transmission Failed"
        severity failure;
      end if;
    end loop;
    wait for (16*CLK_PERIOD);

    -- LCR Intialization
    --   bit 6 : 0, do not set break
    --   bit 5 : 1, stick parity
    --   bit 4 : 0, odd parity selected
    --   bit 3 : 1, parity enabled
    --   bit 2 : 1, 1.5 stop bit
    --   bit 1 : 0, 5 data bit (bit[1-0]="00")
    --   bit 0 : 0, 5 data bit (bit[1-0]="00")
    write_reg (LCR,"00101100",CS,ADSn,WRn,A,DIN);

    -- Write 1st data to THR
    write_reg (THR,"01010101",CS,ADSn,WRn,A,DIN);

    -- Write 2nd data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"10101010",CS,ADSn,WRn,A,DIN);

    -- Write 3rd data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"01011010",CS,ADSn,WRn,A,DIN);

    -- Write 4th data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"10100101",CS,ADSn,WRn,A,DIN);


    wait until falling_edge(PCLK);
    -- Test 9 ----------------------------------------------------
    --   5-bit data, no parity, 1 stop
    TestID <= 9;

    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        -- Read LSR (check if "TEMT" flag at bit 6 is set)
        read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
        exit when regData_readBack(6) = '1';
        i := i + 1;
      else
        assert (false) report"Data Transmission Failed"
        severity failure;
      end if;
    end loop;
    wait for (16*CLK_PERIOD);

    -- LCR Intialization
    --   bit 6 : 0, do not set break
    --   bit 5 : 0, not stick parity
    --   bit 4 : 0, odd parity selected
    --   bit 3 : 0, parity disabled
    --   bit 2 : 0, 1 stop bit
    --   bit 1 : 0, 5 data bit (bit[1-0]="00")
    --   bit 0 : 0, 5 data bit (bit[1-0]="00")
    write_reg (LCR,"00000000",CS,ADSn,WRn,A,DIN);

    -- Write 1st data to THR
    write_reg (THR,"01010101",CS,ADSn,WRn,A,DIN);

    -- Write 2nd data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"10101010",CS,ADSn,WRn,A,DIN);

    -- Write 3rd data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"01011010",CS,ADSn,WRn,A,DIN);

    -- Write 4th data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"10100101",CS,ADSn,WRn,A,DIN);


    wait until falling_edge(PCLK);
?? 文件大小 653 K
?? 上傳用戶 proudrock
?? 所屬分類 VHDL/FPGA/Verilog
??? 相關標簽

#URAT #VHDL #異步通信接口
?? 快捷鍵說明

復制代碼 Ctrl + C
搜索代碼 Ctrl + F
全屏模式 F11
切換主題 Ctrl + Shift + D
顯示快捷鍵 ?
增大字號 Ctrl + =
減小字號 Ctrl + -
亚洲欧美第一页_禁久久精品乱码_粉嫩av一区二区三区免费野_久草精品视频

?? uart_tx_tb.vhd

?? 快捷鍵說明
