Assembler report for UART_top
Sun Mar 30 21:13:54 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Assembler Summary
  3. Assembler Settings
  4. Assembler Generated Files
  5. Assembler Device Options: D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.sof
  6. Assembler Device Options: D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.pof
  7. Assembler Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+---------------------------------------------------------------+
; Assembler Summary                                             ;
+-----------------------+---------------------------------------+
; Assembler Status      ; Successful - Sun Mar 30 21:13:54 2008 ;
; Revision Name         ; UART_top                              ;
; Top-level Entity Name ; Uart_top                              ;
; Family                ; Cyclone II                            ;
; Device                ; EP2C5T144C6                           ;
+-----------------------+---------------------------------------+


+-----------------------------------------------------------------------------------------------------------+
; Assembler Settings                                                                                        ;
+--------------------------------------------------------------------------------+----------+---------------+
; Option                                                                         ; Setting  ; Default Value ;
+--------------------------------------------------------------------------------+----------+---------------+
; Use smart compilation                                                          ; Off      ; Off           ;
; Generate Serial Vector Format File (.svf) for Target Device                    ; Off      ; Off           ;
; Generate a JEDEC STAPL Format File (.jam) for Target Device                    ; Off      ; Off           ;
; Generate an uncompressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off      ; Off           ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device    ; On       ; On            ;
; Generate compressed bitstreams                                                 ; On       ; On            ;
; Compression mode                                                               ; Off      ; Off           ;
; Clock source for configuration device                                          ; Internal ; Internal      ;
; Clock frequency of the configuration device                                    ; 10 MHZ   ; 10 MHz        ;
; Divide clock frequency by                                                      ; 1        ; 1             ;
; JTAG user code for target device                                               ; Ffffffff ; Ffffffff      ;
; Configuration device                                                           ; Auto     ; Auto          ;
; JTAG user code for configuration device                                        ; Ffffffff ; Ffffffff      ;
; Configuration device auto user code                                            ; Off      ; Off           ;
; Generate Tabular Text File (.ttf) For Target Device                            ; Off      ; Off           ;
; Generate Raw Binary File (.rbf) For Target Device                              ; Off      ; Off           ;
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device    ; Off      ; Off           ;
; Hexadecimal Output File start address                                          ; 0        ; 0             ;
; Hexadecimal Output File count direction                                        ; Up       ; Up            ;
; Release clears before tri-states                                               ; Off      ; Off           ;
; Auto-restart configuration after error                                         ; On       ; On            ;
; Maintain Compatibility with All Cyclone II M4K Versions                        ; On       ; On            ;
+--------------------------------------------------------------------------------+----------+---------------+


+----------------------------------------------------+
; Assembler Generated Files                          ;
+----------------------------------------------------+
; File Name                                          ;
+----------------------------------------------------+
; D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.sof ;
; D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.pof ;
+----------------------------------------------------+


+------------------------------------------------------------------------------+
; Assembler Device Options: D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.sof ;
+----------------+-------------------------------------------------------------+
; Option         ; Setting                                                     ;
+----------------+-------------------------------------------------------------+
; Device         ; EP2C5T144C6                                                 ;
; JTAG usercode  ; 0xFFFFFFFF                                                  ;
; Checksum       ; 0x00098F8B                                                  ;
+----------------+-------------------------------------------------------------+


+------------------------------------------------------------------------------+
; Assembler Device Options: D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.pof ;
+----------------+-------------------------------------------------------------+
; Option         ; Setting                                                     ;
+----------------+-------------------------------------------------------------+
; Device         ; EPCS4                                                       ;
; JTAG usercode  ; 0x00000000                                                  ;
; Checksum       ; 0x074D7C3A                                                  ;
+----------------+-------------------------------------------------------------+


+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Assembler
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun Mar 30 21:13:51 2008
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off UART_top -c UART_top
Info: Writing out detailed assembly data for power analysis
Info: Assembler is generating device programming files
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
    Info: Processing ended: Sun Mar 30 21:13:54 2008
    Info: Elapsed time: 00:00:04