{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 30 21:13:32 2008 " "Info: Processing started: Sun Mar 30 21:13:32 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off UART_top -c UART_top " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off UART_top -c UART_top" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "UART_top.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file UART_top.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Uart_top-Uart_top_a " "Info: Found design unit 1: Uart_top-Uart_top_a" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 125 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 Uart_top " "Info: Found entity 1: Uart_top" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 90 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "UART_top " "Info: Elaborating entity \"UART_top\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "Intface.vhd 2 1 " "Warning: Using design file Intface.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Intface-Intface_a " "Info: Found design unit 1: Intface-Intface_a" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 332 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 Intface " "Info: Found entity 1: Intface" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 289 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Intface Intface:U1 " "Info: Elaborating entity \"Intface\" for hierarchy \"Intface:U1\"" {  } { { "UART_top.vhd" "U1" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 267 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "ADDR_s Intface.vhd(398) " "Warning (10631): VHDL Process Statement warning at Intface.vhd(398): inferring latch(es) for signal or variable \"ADDR_s\", which holds its previous value in one or more paths through the process" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 398 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "CS_r Intface.vhd(411) " "Warning (10631): VHDL Process Statement warning at Intface.vhd(411): inferring latch(es) for signal or variable \"CS_r\", which holds its previous value in one or more paths through the process" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 411 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "CS_r Intface.vhd(411) " "Info (10041): Verilog HDL or VHDL info at Intface.vhd(411): inferred latch for \"CS_r\"" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 411 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "ADDR_s\[0\] Intface.vhd(398) " "Info (10041): Verilog HDL or VHDL info at Intface.vhd(398): inferred latch for \"ADDR_s\[0\]\"" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 398 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "ADDR_s\[1\] Intface.vhd(398) " "Info (10041): Verilog HDL or VHDL info at Intface.vhd(398): inferred latch for \"ADDR_s\[1\]\"" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 398 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "ADDR_s\[2\] Intface.vhd(398) " "Info (10041): Verilog HDL or VHDL info at Intface.vhd(398): inferred latch for \"ADDR_s\[2\]\"" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 398 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "Modem.vhd 2 1 " "Warning: Using design file Modem.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Modem-Modem_a " "Info: Found design unit 1: Modem-Modem_a" {  } { { "Modem.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Modem.vhd" 98 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 Modem " "Info: Found entity 1: Modem" {  } { { "Modem.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Modem.vhd" 78 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Modem Modem:U2 " "Info: Elaborating entity \"Modem\" for hierarchy \"Modem:U2\"" {  } { { "UART_top.vhd" "U2" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 308 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "Rxcver.vhd 2 1 " "Warning: Using design file Rxcver.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Rxcver-Rxcver_a " "Info: Found design unit 1: Rxcver-Rxcver_a" {  } { { "Rxcver.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Rxcver.vhd" 112 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 Rxcver " "Info: Found entity 1: Rxcver" {  } { { "Rxcver.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Rxcver.vhd" 86 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Rxcver Rxcver:U3 " "Info: Elaborating entity \"Rxcver\" for hierarchy \"Rxcver:U3\"" {  } { { "UART_top.vhd" "U3" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 326 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}