|UART_top
MR => Txmitt:U4.Reset
MR => Rxcver:U3.Reset
MR => Modem:U2.Reset
MR => Intface:U1.Reset
MCLK => Txmitt:U4.Clk16X
MCLK => Rxcver:U3.Clk16X
MCLK => Modem:U2.Clk16X
MCLK => Intface:U1.Clk16X
A[0] => Intface:U1.A[0]
A[1] => Intface:U1.A[1]
A[2] => Intface:U1.A[2]
DIN[0] => Intface:U1.DIN[0]
DIN[1] => Intface:U1.DIN[1]
DIN[2] => Intface:U1.DIN[2]
DIN[3] => Intface:U1.DIN[3]
DIN[4] => Intface:U1.DIN[4]
DIN[5] => Intface:U1.DIN[5]
DIN[6] => Intface:U1.DIN[6]
DIN[7] => Intface:U1.DIN[7]
DOUT[0] <= Intface:U1.DOUT[0]
DOUT[1] <= Intface:U1.DOUT[1]
DOUT[2] <= Intface:U1.DOUT[2]
DOUT[3] <= Intface:U1.DOUT[3]
DOUT[4] <= Intface:U1.DOUT[4]
DOUT[5] <= Intface:U1.DOUT[5]
DOUT[6] <= Intface:U1.DOUT[6]
DOUT[7] <= Intface:U1.DOUT[7]
ADSn => Intface:U1.ADSn
CS => Intface:U1.CS
RDn => Intface:U1.RDn
WRn => Intface:U1.WRn
DDIS <= Intface:U1.DDIS
INTR <= Intface:U1.INTR
SIN => Rxcver:U3.SIN
RxRDYn <= Rxcver:U3.RxRDY
SOUT <= Txmitt:U4.SOUT
TxRDYn <= Txmitt:U4.THRE
DCDn => Modem:U2.DCDn
CTSn => Modem:U2.CTSn
DSRn => Modem:U2.DSRn
RIn => Modem:U2.RIn
DTRn <= Modem:U2.DTRn
RTSn <= Modem:U2.RTSn


|UART_top|Intface:U1
Reset => ThrWRn_r.OUTPUTSELECT
Reset => RbrRDn_r.OUTPUTSELECT
Reset => LsrRDn_r.OUTPUTSELECT
Reset => MsrRDn_r.OUTPUTSELECT
Reset => IirRDn_r.OUTPUTSELECT
Reset => DOUT~8.OUTPUTSELECT
Reset => DOUT~9.OUTPUTSELECT
Reset => DOUT~10.OUTPUTSELECT
Reset => DOUT~11.OUTPUTSELECT
Reset => DOUT~12.OUTPUTSELECT
Reset => DOUT~13.OUTPUTSELECT
Reset => DOUT~14.OUTPUTSELECT
Reset => DOUT~15.OUTPUTSELECT
Reset => MCR[0]~reg0.ACLR
Reset => MCR[1]~reg0.ACLR
Reset => LCR[0].ACLR
Reset => LCR[1].ACLR
Reset => LCR[2].ACLR
Reset => LCR[3].ACLR
Reset => LCR[4].ACLR
Reset => LCR[5].ACLR
Reset => LCR[6].ACLR
Reset => IER[0].ACLR
Reset => IER[1].ACLR
Reset => IER[2].ACLR
Reset => IER[3].ACLR
Reset => THR[0]~reg0.ACLR
Reset => THR[1]~reg0.ACLR
Reset => THR[2]~reg0.ACLR
Reset => THR[3]~reg0.ACLR
Reset => THR[4]~reg0.ACLR
Reset => THR[5]~reg0.ACLR
Reset => THR[6]~reg0.ACLR
Reset => THR[7]~reg0.ACLR
Reset => IirRDn2_r.PRESET
Reset => IirRDn1_r.PRESET
Reset => MsrRDn2_r.PRESET
Reset => MsrRDn1_r.PRESET
Reset => LsrRDn2_r.PRESET
Reset => LsrRDn1_r.PRESET
Reset => RbrRDn2_r.PRESET
Reset => RbrRDn1_r.PRESET
Reset => ThrWRn2_r.PRESET
Reset => ThrWRn1_r.PRESET
Reset => CS_r.ACLR
Reset => ADDR_s[0].ACLR
Reset => ADDR_s[1].ACLR
Reset => ADDR_s[2].ACLR
Reset => Int_State~41.IN1
Clk16X => IirRDn2_r.CLK
Clk16X => IirRDn1_r.CLK
Clk16X => MsrRDn2_r.CLK
Clk16X => MsrRDn1_r.CLK
Clk16X => LsrRDn2_r.CLK
Clk16X => LsrRDn1_r.CLK
Clk16X => RbrRDn2_r.CLK
Clk16X => RbrRDn1_r.CLK
Clk16X => ThrWRn2_r.CLK
Clk16X => ThrWRn1_r.CLK
Clk16X => Int_State~40.IN1
A[0] => ADDR_s[0].DATAIN
A[1] => ADDR_s[1].DATAIN
A[2] => ADDR_s[2].DATAIN
DIN[0] => Mux15.IN0
DIN[0] => Mux19.IN0
DIN[0] => Mux26.IN0
DIN[0] => Mux28.IN0
DIN[1] => Mux14.IN0
DIN[1] => Mux18.IN0
DIN[1] => Mux25.IN0
DIN[1] => Mux27.IN0
DIN[2] => Mux13.IN0
DIN[2] => Mux17.IN0
DIN[2] => Mux24.IN0
DIN[3] => Mux12.IN0
DIN[3] => Mux16.IN0
DIN[3] => Mux23.IN0
DIN[4] => Mux11.IN0
DIN[4] => Mux22.IN0
DIN[5] => Mux10.IN0
DIN[5] => Mux21.IN0
DIN[6] => Mux9.IN0
DIN[6] => Mux20.IN0
DIN[7] => Mux8.IN0
DOUT[0] <= DOUT~15.DB_MAX_OUTPUT_PORT_TYPE
DOUT[1] <= DOUT~14.DB_MAX_OUTPUT_PORT_TYPE
DOUT[2] <= DOUT~13.DB_MAX_OUTPUT_PORT_TYPE
DOUT[3] <= DOUT~12.DB_MAX_OUTPUT_PORT_TYPE
DOUT[4] <= DOUT~11.DB_MAX_OUTPUT_PORT_TYPE
DOUT[5] <= DOUT~10.DB_MAX_OUTPUT_PORT_TYPE
DOUT[6] <= DOUT~9.DB_MAX_OUTPUT_PORT_TYPE
DOUT[7] <= DOUT~8.DB_MAX_OUTPUT_PORT_TYPE
ADSn => ADDR_s[1].LATCH_ENABLE
ADSn => ADDR_s[2].LATCH_ENABLE
ADSn => ADDR_s[0].LATCH_ENABLE
ADSn => CS_r.LATCH_ENABLE
CS => CS_r.DATAIN
RDn => RDn_cs~0.DATAB
WRn => WRn_cs.DATAB
DDIS <= RDn_cs~0.DB_MAX_OUTPUT_PORT_TYPE
INTR <= INTR~2.DB_MAX_OUTPUT_PORT_TYPE
RBR[0] => Mux7.IN4
RBR[1] => Mux6.IN4
RBR[2] => Mux5.IN4
RBR[3] => Mux4.IN5
RBR[4] => Mux3.IN5
RBR[5] => Mux2.IN5
RBR[6] => Mux1.IN5
RBR[7] => Mux0.IN6
THR[0] <= THR[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
THR[1] <= THR[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
THR[2] <= THR[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
THR[3] <= THR[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
THR[4] <= THR[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
THR[5] <= THR[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
THR[6] <= THR[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
THR[7] <= THR[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
MSR[0] => Mux7.IN5
MSR[0] => ModemStat~0.IN0
MSR[1] => Mux6.IN5
MSR[1] => ModemStat~0.IN1
MSR[2] => Mux5.IN5
MSR[2] => ModemStat~1.IN0
MSR[3] => Mux4.IN6
MSR[3] => ModemStat.IN0
MSR[4] => Mux3.IN6
MSR[5] => Mux2.IN6
MSR[6] => Mux1.IN6
MSR[7] => Mux0.IN7
MCR[0] <= MCR[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
MCR[1] <= MCR[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RbrRDn_re <= RbrRDn_re~0.DB_MAX_OUTPUT_PORT_TYPE
ThrWRn_re <= ThrWRn_re~0.DB_MAX_OUTPUT_PORT_TYPE
LsrRDn_re <= LsrRDn_re~0
MsrRDn_re <= MsrRDn_re~0
Databits[0] <= LCR[0].DB_MAX_OUTPUT_PORT_TYPE
Databits[1] <= LCR[1].DB_MAX_OUTPUT_PORT_TYPE
Stopbits[0] <= Stopbits~2.DB_MAX_OUTPUT_PORT_TYPE
Stopbits[1] <= Stopbits~1.DB_MAX_OUTPUT_PORT_TYPE
ParityEnable <= LCR[3].DB_MAX_OUTPUT_PORT_TYPE
ParityEven <= LCR[4].DB_MAX_OUTPUT_PORT_TYPE
ParityStick <= LCR[5].DB_MAX_OUTPUT_PORT_TYPE
TxBreak <= LCR[6].DB_MAX_OUTPUT_PORT_TYPE
RxRDY => Mux7.IN9
RxRDY => Int_Arbit_Proc~1.IN1
RxRDY => Int_State~25.OUTPUTSELECT
RxRDY => Int_State~26.OUTPUTSELECT
RxRDY => Int_State~27.OUTPUTSELECT
RxRDY => Int_State~28.OUTPUTSELECT
RxRDY => Int_State~29.OUTPUTSELECT
OverrunErr => Mux6.IN9
OverrunErr => DataErr~0.IN0
ParityErr => Mux5.IN9
ParityErr => DataErr~0.IN1
FrameErr => Mux4.IN10
FrameErr => DataErr~1.IN0
BreakInt => Mux3.IN10
BreakInt => DataErr.IN0
THRE => Mux2.IN10
THRE => Int_Arbit_Proc~2.IN1
THRE => Int_Arbit_Proc~4.IN0
TEMT => Mux1.IN10


|UART_top|Modem:U2
Reset => RIn1.PRESET
Reset => DCDn1.PRESET
Reset => DSRn1.PRESET
Reset => CTSn1.PRESET
Reset => MSReg[0].ACLR
Reset => MSReg[1].ACLR
Reset => MSReg[2].ACLR
Reset => MSReg[3].ACLR
Reset => MSReg[4].ACLR
Reset => MSReg[5].ACLR
Reset => MSReg[6].ACLR
Reset => MSReg[7].ACLR
Clk16X => RIn1.CLK
Clk16X => DCDn1.CLK
Clk16X => DSRn1.CLK
Clk16X => CTSn1.CLK
Clk16X => MSReg[0].CLK
Clk16X => MSReg[1].CLK
Clk16X => MSReg[2].CLK
Clk16X => MSReg[3].CLK
Clk16X => MSReg[4].CLK
Clk16X => MSReg[5].CLK
Clk16X => MSReg[6].CLK
Clk16X => MSReg[7].CLK
MSR[0] <= MSReg[0].DB_MAX_OUTPUT_PORT_TYPE
MSR[1] <= MSReg[1].DB_MAX_OUTPUT_PORT_TYPE
MSR[2] <= MSReg[2].DB_MAX_OUTPUT_PORT_TYPE
MSR[3] <= MSReg[3].DB_MAX_OUTPUT_PORT_TYPE
MSR[4] <= MSReg[4].DB_MAX_OUTPUT_PORT_TYPE
MSR[5] <= MSReg[5].DB_MAX_OUTPUT_PORT_TYPE
MSR[6] <= MSReg[6].DB_MAX_OUTPUT_PORT_TYPE
MSR[7] <= MSReg[7].DB_MAX_OUTPUT_PORT_TYPE
MCR[0] => DTRn.DATAIN
MCR[1] => RTSn.DATAIN
MsrRDn_re => MSReg~8.OUTPUTSELECT
MsrRDn_re => MSReg~9.OUTPUTSELECT
MsrRDn_re => MSReg~10.OUTPUTSELECT
MsrRDn_re => MSReg~11.OUTPUTSELECT
MsrRDn_re => MSReg~12.OUTPUTSELECT
MsrRDn_re => MSReg~13.OUTPUTSELECT
MsrRDn_re => MSReg~14.OUTPUTSELECT
MsrRDn_re => MSReg~15.OUTPUTSELECT
DCDn => MSReg~6.IN1
DCDn => DCDn1.DATAIN
DCDn => MSReg~8.DATAA
CTSn => MSReg~0.IN1
CTSn => CTSn1.DATAIN
CTSn => MSReg~11.DATAA
DSRn => MSReg~2.IN1
DSRn => DSRn1.DATAIN
DSRn => MSReg~10.DATAA
RIn => MSReg~4.IN1
RIn => RIn1.DATAIN
RIn => MSReg~9.DATAA
DTRn <= MCR[0].DB_MAX_OUTPUT_PORT_TYPE
RTSn <= MCR[1].DB_MAX_OUTPUT_PORT_TYPE


|UART_top|Rxcver:U3
Reset => BreakInt_r.ACLR
Reset => FrameErr_r.ACLR
Reset => ParityErr_r.ACLR
Reset => OverrunErr_r.ACLR
Reset => RxIdle1_r.PRESET
Reset => RxFrmErr1_r.PRESET
Reset => SIN1_r.ACLR
Reset => RBR_r[0].ACLR
Reset => RBR_r[1].ACLR
Reset => RBR_r[2].ACLR
Reset => RBR_r[3].ACLR
Reset => RBR_r[4].ACLR
Reset => RBR_r[5].ACLR
Reset => RBR_r[6].ACLR
Reset => RBR_r[7].ACLR
Reset => RxFrmErr.ACLR
Reset => RxPrtyErr.PRESET
Reset => NumDataBitReceived_r[0].ACLR
Reset => NumDataBitReceived_r[1].ACLR
Reset => NumDataBitReceived_r[2].ACLR
Reset => NumDataBitReceived_r[3].ACLR
Reset => RSR[0].ACLR
Reset => RSR[1].ACLR
Reset => RSR[2].ACLR
Reset => RSR[3].ACLR
Reset => RSR[4].ACLR
Reset => RSR[5].ACLR
Reset => RSR[6].ACLR
Reset => RSR[7].ACLR
Reset => RxIdle_r.PRESET
Reset => SampledOnce.ACLR
Reset => RbrDataRDY.ACLR
Reset => HuntOne_r.ACLR
Reset => Hunt_r.ACLR
Reset => CNT_r[0].ACLR
Reset => CNT_r[1].ACLR
Reset => CNT_r[2].ACLR
Reset => CNT_r[3].ACLR
Reset => RxClkEn.ACLR
Reset => Rx_State~19.IN1
Clk16X => BreakInt_r.CLK
Clk16X => FrameErr_r.CLK
Clk16X => ParityErr_r.CLK
Clk16X => OverrunErr_r.CLK
Clk16X => RxIdle1_r.CLK
Clk16X => RxFrmErr1_r.CLK
Clk16X => SIN1_r.CLK
Clk16X => RBR_r[0].CLK
Clk16X => RBR_r[1].CLK
Clk16X => RBR_r[2].CLK
Clk16X => RBR_r[3].CLK
Clk16X => RBR_r[4].CLK
Clk16X => RBR_r[5].CLK
Clk16X => RBR_r[6].CLK
Clk16X => RBR_r[7].CLK
Clk16X => RxFrmErr.CLK
Clk16X => RxPrtyErr.CLK
Clk16X => NumDataBitReceived_r[0].CLK
Clk16X => NumDataBitReceived_r[1].CLK
Clk16X => NumDataBitReceived_r[2].CLK
Clk16X => NumDataBitReceived_r[3].CLK
Clk16X => RSR[0].CLK
Clk16X => RSR[1].CLK
Clk16X => RSR[2].CLK
Clk16X => RSR[3].CLK
Clk16X => RSR[4].CLK
Clk16X => RSR[5].CLK
Clk16X => RSR[6].CLK
Clk16X => RSR[7].CLK
Clk16X => RxIdle_r.CLK
Clk16X => SampledOnce.CLK
Clk16X => RbrDataRDY.CLK
Clk16X => HuntOne_r.CLK
Clk16X => Hunt_r.CLK
Clk16X => CNT_r[0].CLK
Clk16X => CNT_r[1].CLK
Clk16X => CNT_r[2].CLK
Clk16X => CNT_r[3].CLK
Clk16X => RxClkEn.CLK
Clk16X => Rx_State~18.IN1
RBR[0] <= RBR_r[0].DB_MAX_OUTPUT_PORT_TYPE
RBR[1] <= RBR_r[1].DB_MAX_OUTPUT_PORT_TYPE
RBR[2] <= RBR_r[2].DB_MAX_OUTPUT_PORT_TYPE
RBR[3] <= RBR_r[3].DB_MAX_OUTPUT_PORT_TYPE
RBR[4] <= RBR_r[4].DB_MAX_OUTPUT_PORT_TYPE
RBR[5] <= RBR_r[5].DB_MAX_OUTPUT_PORT_TYPE
RBR[6] <= RBR_r[6].DB_MAX_OUTPUT_PORT_TYPE
RBR[7] <= RBR_r[7].DB_MAX_OUTPUT_PORT_TYPE
RbrRDn_re => RbrDataRDY~0.OUTPUTSELECT
LsrRDn_re => OverrunErr_r~0.OUTPUTSELECT
LsrRDn_re => ParityErr_r~2.OUTPUTSELECT
LsrRDn_re => FrameErr_r~1.OUTPUTSELECT
LsrRDn_re => BreakInt_r~1.OUTPUTSELECT
SIN => Hunt_r_Proc~3.IN1
SIN => HuntOne_r_Proc~1.IN0
SIN => RxPrtyErr~1.IN1
SIN => RSR~8.DATAB
SIN => RxPrtyErr~3.DATAB
SIN => SIN1_r.DATAIN
SIN => Shift_data_Proc~0.IN1
SIN => RxFrmErr~1.DATAB
SIN => RxPrtyErr~3.DATAA
SIN => SampledOnce_Proc~1.IN0
SIN => Hunt_r_Proc~2.IN1
SIN => Hunt_r_Proc~0.IN1
Databits[0] => Equal1.IN3
Databits[0] => Equal3.IN3
Databits[0] => Equal5.IN3
Databits[0] => Equal7.IN3
Databits[0] => Mux0.IN4
Databits[0] => Mux1.IN3
Databits[0] => Mux2.IN2
Databits[0] => Mux3.IN1
Databits[0] => Mux4.IN1
Databits[0] => Mux5.IN1
Databits[0] => Mux6.IN1
Databits[0] => Mux7.IN1
Databits[1] => Equal1.IN2
Databits[1] => Equal3.IN2
Databits[1] => Equal5.IN2
Databits[1] => Equal7.IN2
Databits[1] => Mux0.IN3
Databits[1] => Mux1.IN2
Databits[1] => Mux2.IN1
Databits[1] => Mux3.IN0
Databits[1] => Mux4.IN0
Databits[1] => Mux5.IN0
Databits[1] => Mux6.IN0
Databits[1] => Mux7.IN0
ParityEnable => Rx_State~6.DATAB
ParityEnable => ParityErr_r~1.IN1
ParityEnable => Rx_State~7.DATAB
ParityEven => RxPrtyErr~3.OUTPUTSELECT
ParityEven => RxPrtyErr~0.DATAB
ParityStick => RxPrtyErr~4.OUTPUTSELECT
RxRDY <= RbrDataRDY.DB_MAX_OUTPUT_PORT_TYPE
OverrunErr <= OverrunErr_r.DB_MAX_OUTPUT_PORT_TYPE
ParityErr <= ParityErr_r.DB_MAX_OUTPUT_PORT_TYPE
FrameErr <= FrameErr_r.DB_MAX_OUTPUT_PORT_TYPE
BreakInt <= BreakInt_r.DB_MAX_OUTPUT_PORT_TYPE


|UART_top|Txmitt:U4
Reset => TxClkEnB.ACLR
Reset => TxClkEnA.ACLR
Reset => Count_vr[0].PRESET
Reset => Count_vr[1].PRESET
Reset => Count_vr[2].PRESET
Reset => Count_vr[3].PRESET
Reset => TxInStartState.ACLR
Reset => TxInStopState.ACLR
Reset => TxInShiftState.ACLR
Reset => TxInStopState1.PRESET
Reset => TxInShiftState1.PRESET
Reset => TxInStartState1.PRESET
Reset => ThrEmpty.PRESET
Reset => TsrEmpty.PRESET
Reset => TxParity_r.PRESET
Reset => TxOutput.PRESET
Reset => TSR[0].ACLR
Reset => TSR[1].ACLR
Reset => TSR[2].ACLR
Reset => TSR[3].ACLR
Reset => TSR[4].ACLR
Reset => TSR[5].ACLR
Reset => TSR[6].ACLR
Reset => TSR[7].ACLR
Reset => TxCNT_r[0].ACLR
Reset => TxCNT_r[1].ACLR
Reset => TxCNT_r[2].ACLR
Reset => Tx_State~38.IN1
Clk16X => TxClkEnB.CLK
Clk16X => TxClkEnA.CLK
Clk16X => Count_vr[0].CLK
Clk16X => Count_vr[1].CLK
Clk16X => Count_vr[2].CLK
Clk16X => Count_vr[3].CLK
Clk16X => TxInStartState.CLK
Clk16X => TxInStopState.CLK
Clk16X => TxInShiftState.CLK
Clk16X => TxInStopState1.CLK
Clk16X => TxInShiftState1.CLK
Clk16X => TxInStartState1.CLK
Clk16X => ThrEmpty.CLK
Clk16X => TsrEmpty.CLK
Clk16X => TxParity_r.CLK
Clk16X => TxOutput.CLK
Clk16X => TSR[0].CLK
Clk16X => TSR[1].CLK
Clk16X => TSR[2].CLK
Clk16X => TSR[3].CLK
Clk16X => TSR[4].CLK
Clk16X => TSR[5].CLK
Clk16X => TSR[6].CLK
Clk16X => TSR[7].CLK
Clk16X => TxCNT_r[0].CLK
Clk16X => TxCNT_r[1].CLK
Clk16X => TxCNT_r[2].CLK
Clk16X => Tx_State~37.IN1
THR[0] => TSR~7.DATAB
THR[1] => TSR~6.DATAB
THR[2] => TSR~5.DATAB
THR[3] => TSR~4.DATAB
THR[4] => TSR~3.DATAB
THR[5] => TSR~2.DATAB
THR[6] => TSR~1.DATAB
THR[7] => TSR~0.DATAB
ThrWRn_re => ThrEmpty~1.OUTPUTSELECT
SOUT <= SOUT~0.DB_MAX_OUTPUT_PORT_TYPE
DataBits[0] => Equal0.IN3
DataBits[0] => Equal2.IN3
DataBits[0] => Equal4.IN3
DataBits[0] => Equal6.IN3
DataBits[1] => Equal0.IN2
DataBits[1] => Equal2.IN2
DataBits[1] => Equal4.IN2
DataBits[1] => Equal6.IN2
StopBits[0] => Equal8.IN3
StopBits[0] => Equal9.IN3
StopBits[1] => Equal8.IN2
StopBits[1] => Equal9.IN2
ParityEnable => Tx_State~8.DATAB
ParityEnable => Tx_State~9.DATAB
ParityEven => TxParity_r~0.DATAB
ParityEven => TxOutput~1.DATAB
ParityStick => TxOutput~1.OUTPUTSELECT
TxBreak => SOUT~0.OUTPUTSELECT
THRE <= ThrEmpty.DB_MAX_OUTPUT_PORT_TYPE
TEMT <= TEMT~0.DB_MAX_OUTPUT_PORT_TYPE