module claslice_0 ( Port1, Port2, Port3, Port4, Port5, Port6, Port7, Port8, Co,         Port9, Port10, Port11, pp, gg );  input Port1, Port2, Port3, Port4, Port5, Port6, Port7, Port8, Co;  output Port9, Port10, Port11, pp, gg;  wire   n6, n7, n8, n9, n10, n11, n12;  wire   [3:0] p;  wire   [3:0] g;  wire   [2:0] Cp;  assign p[3] = Port1;  assign p[2] = Port2;  assign p[1] = Port3;  assign p[0] = Port4;  assign g[3] = Port5;  assign g[2] = Port6;  assign g[1] = Port7;  assign g[0] = Port8;  assign Port9 = Cp[2];  assign Port10 = Cp[1];  assign Port11 = Cp[0];  OAI21XL U1 ( .A0(n11), .A1(n9), .B0(n10), .Y(Cp[2]) );  INVX1 U2 ( .A(p[2]), .Y(n9) );  INVX1 U3 ( .A(n11), .Y(Cp[1]) );  AOI21X1 U4 ( .A0(Cp[0]), .A1(p[1]), .B0(g[1]), .Y(n11) );  OAI21XL U5 ( .A0(n8), .A1(n9), .B0(n10), .Y(n7) );  AOI21X1 U6 ( .A0(g[0]), .A1(p[1]), .B0(g[1]), .Y(n8) );  INVX1 U7 ( .A(g[2]), .Y(n10) );  INVX1 U8 ( .A(n6), .Y(gg) );  AND4X2 U9 ( .A(p[3]), .B(p[2]), .C(p[1]), .D(p[0]), .Y(pp) );  AOI21X1 U10 ( .A0(p[3]), .A1(n7), .B0(g[3]), .Y(n6) );  INVX1 U11 ( .A(n12), .Y(Cp[0]) );  AOI21X1 U12 ( .A0(Co), .A1(p[0]), .B0(g[0]), .Y(n12) );endmodulemodule claslice5_0 ( Port12, Port13, Port14, Port15, Port16, Port17, Port18,         Port19, Port20, Port21, Co, Port22, Port23, Port24, Port25, pp, gg );  input Port12, Port13, Port14, Port15, Port16, Port17, Port18, Port19, Port20,         Port21, Co;  output Port22, Port23, Port24, Port25, pp, gg;  wire   n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20;  wire   [4:0] p;  wire   [4:0] g;  wire   [3:0] Cp;  assign p[4] = Port12;  assign p[3] = Port13;  assign p[2] = Port14;  assign p[1] = Port15;  assign p[0] = Port16;  assign g[4] = Port17;  assign g[3] = Port18;  assign g[2] = Port19;  assign g[1] = Port20;  assign g[0] = Port21;  assign Port22 = Cp[3];  assign Port23 = Cp[2];  assign Port24 = Cp[1];  assign Port25 = Cp[0];  NOR3X1 U1 ( .A(n9), .B(n10), .C(n11), .Y(pp) );  NAND3X1 U2 ( .A(p[1]), .B(p[0]), .C(p[2]), .Y(n9) );  AOI21X1 U3 ( .A0(Cp[1]), .A1(p[2]), .B0(g[2]), .Y(n17) );  OAI21XL U4 ( .A0(n17), .A1(n10), .B0(n18), .Y(Cp[3]) );  INVX1 U5 ( .A(g[3]), .Y(n18) );  INVX1 U6 ( .A(n17), .Y(Cp[2]) );  AOI21X1 U7 ( .A0(n15), .A1(p[2]), .B0(g[2]), .Y(n14) );  INVX1 U8 ( .A(n16), .Y(n15) );  AOI21X1 U9 ( .A0(g[0]), .A1(p[1]), .B0(g[1]), .Y(n16) );  INVX1 U10 ( .A(p[3]), .Y(n10) );  INVX1 U11 ( .A(n19), .Y(Cp[1]) );  AOI21X1 U12 ( .A0(Cp[0]), .A1(p[1]), .B0(g[1]), .Y(n19) );  INVX1 U13 ( .A(p[4]), .Y(n11) );  OAI21XL U14 ( .A0(n12), .A1(n11), .B0(n13), .Y(gg) );  INVX1 U15 ( .A(g[4]), .Y(n13) );  AOI2BB1X1 U16 ( .A0N(n10), .A1N(n14), .B0(g[3]), .Y(n12) );  INVX1 U17 ( .A(n20), .Y(Cp[0]) );  AOI21X1 U18 ( .A0(Co), .A1(p[0]), .B0(g[0]), .Y(n20) );endmodulemodule pg20_0 ( a, b, p, g );  input [19:0] a;  input [19:0] b;  output [19:0] p;  output [19:0] g;  XOR2X1 U1 ( .A(b[6]), .B(a[6]), .Y(p[6]) );  XOR2X1 U2 ( .A(b[11]), .B(a[11]), .Y(p[11]) );  XOR2X1 U3 ( .A(b[1]), .B(a[1]), .Y(p[1]) );  XOR2X1 U4 ( .A(b[16]), .B(a[16]), .Y(p[16]) );  XOR2X1 U5 ( .A(b[7]), .B(a[7]), .Y(p[7]) );  XOR2X1 U6 ( .A(b[12]), .B(a[12]), .Y(p[12]) );  XOR2X1 U7 ( .A(b[2]), .B(a[2]), .Y(p[2]) );  XOR2X1 U8 ( .A(b[17]), .B(a[17]), .Y(p[17]) );  AND2X2 U9 ( .A(b[4]), .B(a[4]), .Y(g[4]) );  AND2X2 U10 ( .A(b[9]), .B(a[9]), .Y(g[9]) );  XOR2X1 U11 ( .A(b[15]), .B(a[15]), .Y(p[15]) );  XOR2X1 U12 ( .A(b[10]), .B(a[10]), .Y(p[10]) );  XOR2X1 U13 ( .A(b[5]), .B(a[5]), .Y(p[5]) );  XOR2X1 U14 ( .A(b[0]), .B(a[0]), .Y(p[0]) );  XOR2X1 U15 ( .A(b[4]), .B(a[4]), .Y(p[4]) );  XOR2X1 U16 ( .A(b[14]), .B(a[14]), .Y(p[14]) );  XOR2X1 U17 ( .A(b[9]), .B(a[9]), .Y(p[9]) );  XOR2X1 U18 ( .A(b[19]), .B(a[19]), .Y(p[19]) );  XOR2X1 U19 ( .A(b[8]), .B(a[8]), .Y(p[8]) );  XOR2X1 U20 ( .A(b[13]), .B(a[13]), .Y(p[13]) );  XOR2X1 U21 ( .A(b[3]), .B(a[3]), .Y(p[3]) );  XOR2X1 U22 ( .A(b[18]), .B(a[18]), .Y(p[18]) );  AND2X2 U23 ( .A(b[3]), .B(a[3]), .Y(g[3]) );  AND2X2 U24 ( .A(b[13]), .B(a[13]), .Y(g[13]) );  AND2X2 U25 ( .A(b[8]), .B(a[8]), .Y(g[8]) );  AND2X2 U26 ( .A(b[18]), .B(a[18]), .Y(g[18]) );  AND2X2 U27 ( .A(b[0]), .B(a[0]), .Y(g[0]) );  AND2X2 U28 ( .A(b[10]), .B(a[10]), .Y(g[10]) );  AND2X2 U29 ( .A(b[5]), .B(a[5]), .Y(g[5]) );  AND2X2 U30 ( .A(b[15]), .B(a[15]), .Y(g[15]) );  AND2X2 U31 ( .A(b[1]), .B(a[1]), .Y(g[1]) );  AND2X2 U32 ( .A(b[11]), .B(a[11]), .Y(g[11]) );  AND2X2 U33 ( .A(b[6]), .B(a[6]), .Y(g[6]) );  AND2X2 U34 ( .A(b[2]), .B(a[2]), .Y(g[2]) );  AND2X2 U35 ( .A(b[12]), .B(a[12]), .Y(g[12]) );  AND2X2 U36 ( .A(b[7]), .B(a[7]), .Y(g[7]) );  AND2X2 U37 ( .A(b[16]), .B(a[16]), .Y(g[16]) );  AND2X2 U38 ( .A(b[17]), .B(a[17]), .Y(g[17]) );  AND2X2 U39 ( .A(b[19]), .B(a[19]), .Y(g[19]) );  AND2X2 U40 ( .A(b[14]), .B(a[14]), .Y(g[14]) );endmodulemodule cla20_conb_0 ( a, b, cin, s, cout );  input [19:0] a;  input [19:0] b;  output [20:0] s;  input cin;  output cout;  wire   pp1, gg1, pp2, gg2, pp3, gg3, pp4, gg4, pp5, gg5, n2;  wire   [19:0] bb;  wire   [19:0] p;  wire   [19:0] g;  wire   [18:0] Cp;  assign s[20] = 1'b0;  pg20_0 i0 ( .a(a), .b(bb), .p(p), .g(g) );  claslice5_0 i1 ( .Port12(p[4]), .Port13(p[3]), .Port14(p[2]), .Port15(p[1]),         .Port16(p[0]), .Port17(g[4]), .Port18(g[3]), .Port19(g[2]), .Port20(        g[1]), .Port21(g[0]), .Co(cin), .Port22(Cp[3]), .Port23(Cp[2]),         .Port24(Cp[1]), .Port25(Cp[0]), .pp(pp1), .gg(gg1) );  claslice5_15 i2 ( .Port12(p[9]), .Port13(p[8]), .Port14(p[7]), .Port15(p[6]),         .Port16(p[5]), .Port17(g[9]), .Port18(g[8]), .Port19(g[7]), .Port20(        g[6]), .Port21(g[5]), .Co(Cp[4]), .Port22(Cp[8]), .Port23(Cp[7]),         .Port24(Cp[6]), .Port25(Cp[5]), .pp(pp2), .gg(gg2) );  claslice5_14 i3 ( .Port12(p[14]), .Port13(p[13]), .Port14(p[12]), .Port15(        p[11]), .Port16(p[10]), .Port17(g[14]), .Port18(g[13]), .Port19(g[12]),         .Port20(g[11]), .Port21(g[10]), .Co(Cp[9]), .Port22(Cp[13]), .Port23(        Cp[12]), .Port24(Cp[11]), .Port25(Cp[10]), .pp(pp3), .gg(gg3) );  claslice5_13 i4 ( .Port12(p[19]), .Port13(p[18]), .Port14(p[17]), .Port15(        p[16]), .Port16(p[15]), .Port17(g[19]), .Port18(g[18]), .Port19(g[17]),         .Port20(g[16]), .Port21(g[15]), .Co(Cp[14]), .Port22(Cp[18]), .Port23(        Cp[17]), .Port24(Cp[16]), .Port25(Cp[15]), .pp(pp4), .gg(gg4) );  claslice_0 i5 ( .Port1(pp4), .Port2(pp3), .Port3(pp2), .Port4(pp1), .Port5(        gg4), .Port6(gg3), .Port7(gg2), .Port8(gg1), .Co(cin), .Port9(Cp[14]),         .Port10(Cp[9]), .Port11(Cp[4]), .pp(pp5), .gg(gg5) );  XOR2X1 U2 ( .A(p[17]), .B(Cp[16]), .Y(s[17]) );  XOR2X1 U3 ( .A(p[16]), .B(Cp[15]), .Y(s[16]) );  XOR2X1 U4 ( .A(p[12]), .B(Cp[11]), .Y(s[12]) );  XOR2X1 U5 ( .A(p[11]), .B(Cp[10]), .Y(s[11]) );  XOR2X1 U6 ( .A(p[7]), .B(Cp[6]), .Y(s[7]) );  XOR2X1 U7 ( .A(p[6]), .B(Cp[5]), .Y(s[6]) );  XOR2X1 U8 ( .A(p[2]), .B(Cp[1]), .Y(s[2]) );  XOR2X1 U9 ( .A(p[1]), .B(Cp[0]), .Y(s[1]) );  XOR2X1 U10 ( .A(p[15]), .B(Cp[14]), .Y(s[15]) );  XOR2X1 U11 ( .A(p[10]), .B(Cp[9]), .Y(s[10]) );  XOR2X1 U12 ( .A(p[5]), .B(Cp[4]), .Y(s[5]) );  XOR2X1 U13 ( .A(p[19]), .B(Cp[18]), .Y(s[19]) );  XOR2X1 U14 ( .A(p[18]), .B(Cp[17]), .Y(s[18]) );  XOR2X1 U15 ( .A(p[14]), .B(Cp[13]), .Y(s[14]) );  XOR2X1 U16 ( .A(p[13]), .B(Cp[12]), .Y(s[13]) );  XOR2X1 U17 ( .A(p[9]), .B(Cp[8]), .Y(s[9]) );  XOR2X1 U18 ( .A(p[8]), .B(Cp[7]), .Y(s[8]) );  XOR2X1 U19 ( .A(p[4]), .B(Cp[3]), .Y(s[4]) );  XOR2X1 U20 ( .A(p[3]), .B(Cp[2]), .Y(s[3]) );  INVX1 U21 ( .A(n2), .Y(cout) );  XOR2X1 U22 ( .A(p[0]), .B(cin), .Y(s[0]) );  XOR2X1 U23 ( .A(cin), .B(b[0]), .Y(bb[0]) );  XOR2X1 U24 ( .A(cin), .B(b[1]), .Y(bb[1]) );  XOR2X1 U25 ( .A(cin), .B(b[10]), .Y(bb[10]) );  XOR2X1 U26 ( .A(cin), .B(b[11]), .Y(bb[11]) );  XOR2X1 U27 ( .A(cin), .B(b[5]), .Y(bb[5]) );  XOR2X1 U28 ( .A(cin), .B(b[6]), .Y(bb[6]) );  XOR2X1 U29 ( .A(cin), .B(b[2]), .Y(bb[2]) );  XOR2X1 U30 ( .A(cin), .B(b[3]), .Y(bb[3]) );  XOR2X1 U31 ( .A(cin), .B(b[4]), .Y(bb[4]) );  XOR2X1 U32 ( .A(cin), .B(b[12]), .Y(bb[12]) );  XOR2X1 U33 ( .A(cin), .B(b[7]), .Y(bb[7]) );  XOR2X1 U34 ( .A(cin), .B(b[13]), .Y(bb[13]) );  XOR2X1 U35 ( .A(cin), .B(b[14]), .Y(bb[14]) );  XOR2X1 U36 ( .A(cin), .B(b[8]), .Y(bb[8]) );  XOR2X1 U37 ( .A(cin), .B(b[9]), .Y(bb[9]) );  XOR2X1 U38 ( .A(cin), .B(b[15]), .Y(bb[15]) );  XOR2X1 U39 ( .A(cin), .B(b[16]), .Y(bb[16]) );  XOR2X1 U40 ( .A(cin), .B(b[17]), .Y(bb[17]) );  XOR2X1 U41 ( .A(cin), .B(b[18]), .Y(bb[18]) );  XOR2X1 U42 ( .A(cin), .B(b[19]), .Y(bb[19]) );  AOI21X1 U43 ( .A0(pp5), .A1(cin), .B0(gg5), .Y(n2) );endmodulemodule fsm ( clk, rst, read, in1, in2, out1, out2, out3, out4 );  input [18:0] in1;  input [18:0] in2;  output [20:0] out1;  output [20:0] out2;  output [20:0] out3;  output [20:0] out4;  input clk, rst, read;  wire   cin2, cin4, N9, N10, N19, N20, N21, N22, N23, N24, N25, N26, N27, N28,         N29, N30, N31, N32, N33, N34, N35, N36, N37, N38, N39, N40, N41, N42,         N43, N44, N45, N46, N47, N48, N49, N50, N51, N52, N53, N54, N55, N56,         N57, N58, N59, N60, N61, N62, N63, N64, N65, N66, N67, N68, N69, N70,         N71, N72, N73, N74, N75, N76, N77, N78, N79, N80, N81, N82, N83, N84,         N85, N86, N87, N88, N89, N90, N91, N92, N93, N94, N95, N96, N98, N99,         N178, N179, N180, N181, N182, n446, n447, n448, n449, n450, n451,         n452, n453, n454, n455, n456, n457, n458, n459, n460, n461, n462,         n463, n464, n465, n466, n467, n468, n469, n470, n471, n472, n473,         n474, n475, n476, n477, n478, n479, n480, n481, n482, n483, n484,         n485, n486, n487, n488, n489, n490, n491, n492, n493, n494, n495,         n496, n497, n498, n499, n500, n501, n502, n503, n504, n505, n506,         n507, n508, n509, n510, n511, n512, n513, n514, n515, n516, n517,         n518, n519, n520, n521, n522, n523, n524, n525, n526, n527, n528,         n529, n530, n531, n532, n533, n534, n535, n536, n537, n538, n539,         n540, n566, n982, n983, n984, n985, n986, n987, n988, n989, n990,         n991, n992, n993, n994, n995, n996, n997, n998, n999, n1000, n1001,         n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009, n1010, n1011,         n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019, n1020, n1021,         n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029, n1030, n1031,         n1032, n1033;  wire   [19:0] x1;  wire   [19:0] y1;  wire   [20:0] s1;  wire   [19:0] x2;  wire   [19:0] y2;  wire   [20:0] s2;  wire   [19:0] x3;  wire   [19:0] y3;  wire   [20:0] s3;  wire   [19:0] x4;  wire   [19:0] y4;  wire   [20:0] s4;  wire   [2:0] state;  wire   [19:0] R1;  wire   [19:0] R2;  wire   [19:0] R3;  wire   [19:0] buffer1;  wire   [19:0] R4;  wire   [19:0] buffer2;  wire   [19:0] R5;  wire   [19:0] R8;  wire   [19:0] R6;  wire   [19:0] R7;  wire   SYNOPSYS_UNCONNECTED__0, SYNOPSYS_UNCONNECTED__1,         SYNOPSYS_UNCONNECTED__2, SYNOPSYS_UNCONNECTED__3;  assign out1[20] = 1'b0;  assign out2[20] = 1'b0;  assign out3[20] = 1'b0;  assign out4[20] = 1'b0;  cla20_conb_0 adder1 ( .a(x1), .b(y1), .cin(1'b0), .s({        SYNOPSYS_UNCONNECTED__0, s1[19:0]}) );  cla20_conb_3 adder2 ( .a(x2), .b(y2), .cin(cin2), .s({        SYNOPSYS_UNCONNECTED__1, s2[19:0]}) );  cla20_conb_2 adder3 ( .a(x3), .b(y3), .cin(1'b1), .s({        SYNOPSYS_UNCONNECTED__2, s3[19:0]}) );  cla20_conb_1 adder4 ( .a(x4), .b(y4), .cin(cin4), .s({        SYNOPSYS_UNCONNECTED__3, s4[19:0]}) );  TLATX1 \R6_reg[19]  ( .G(n1008), .D(s4[19]), .Q(R6[19]) );  TLATX1 \R5_reg[19]  ( .G(n1006), .D(s3[19]), .Q(R5[19]) );  TLATX1 \R3_reg[0]  ( .G(n1008), .D(s1[0]), .Q(R3[0]) );  TLATX1 \R3_reg[1]  ( .G(N180), .D(s1[1]), .Q(R3[1]) );  TLATX1 \R3_reg[2]  ( .G(N180), .D(s1[2]), .Q(R3[2]) );  TLATX1 \R3_reg[3]  ( .G(N180), .D(s1[3]), .Q(R3[3]) );  TLATX1 \R3_reg[4]  ( .G(n1006), .D(s1[4]), .Q(R3[4]) );  TLATX1 \R3_reg[5]  ( .G(n1007), .D(s1[5]), .Q(R3[5]) );  TLATX1 \R3_reg[6]  ( .G(n1009), .D(s1[6]), .Q(R3[6]) );  TLATX1 \R3_reg[7]  ( .G(n1006), .D(s1[7]), .Q(R3[7]) );  TLATX1 \R3_reg[8]  ( .G(n1010), .D(s1[8]), .Q(R3[8]) );  TLATX1 \R3_reg[9]  ( .G(n1010), .D(s1[9]), .Q(R3[9]) );  TLATX1 \R3_reg[10]  ( .G(n1010), .D(s1[10]), .Q(R3[10]) );  TLATX1 \R3_reg[11]  ( .G(n1010), .D(s1[11]), .Q(R3[11]) );  TLATX1 \R3_reg[12]  ( .G(n1010), .D(s1[12]), .Q(R3[12]) );  TLATX1 \R3_reg[13]  ( .G(n1010), .D(s1[13]), .Q(R3[13]) );  TLATX1 \R3_reg[14]  ( .G(n1010), .D(s1[14]), .Q(R3[14]) );  TLATX1 \R3_reg[15]  ( .G(n1010), .D(s1[15]), .Q(R3[15]) );  TLATX1 \R3_reg[16]  ( .G(n1010), .D(s1[16]), .Q(R3[16]) );  TLATX1 \R3_reg[17]  ( .G(n1010), .D(s