// top.v
//雙端口的RAM初試化采用外部輸入，將0-19填入1-20的值，用于仿真測試，所以頂層也沒有將輸入端口引出，直接進行讀操作
module top(clk,reset,ADDRA,ADDRB,RWA,RWB,CLKA,CLKB,DOUTA,DOUTB);

input clk;
input reset;
output [4:0] ADDRA,ADDRB;
output [7:0] DOUTA,DOUTB;
output RWA,RWB,CLKA,CLKB;
wire   BLKA,BLKB;

Doul_RAM Doul_RAM1(
                   .DINA(),
                   .DOUTA(DOUTA),
                   .DINB(),
                   .DOUTB(DOUTB),
                   .ADDRA(ADDRA),
                   .ADDRB(ADDRB),
                   .RWA(RWA),
                   .RWB(RWB),
                   .BLKA(BLKA),
                   .BLKB(BLKB),
                   .CLKA(CLKA),
                   .CLKB(CLKB)
                   );
read_wirte_ram read_wirte_ram1(
                               .clk(clk),
                               .reset(reset),
                               .ADDRA(ADDRA),
                               .ADDRB(ADDRB),
                               .RWA(RWA),
                               .RWB(RWB),
                               .BLKA(BLKA),
                               .BLKB(BLKB),
                               .CLKA(CLKA),
                               .CLKB(CLKB)
                               );
endmodule