library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity M_generate is
generic(D : integer := 4;
		code_period : integer := 99);
--  31位M序列0000 1010 1110 1100 0111 1100 1101 001
	port(clk : in std_logic;
--	load : in std_logic;--實際板子沒復位信號
	Q : out std_logic);
end M_generate;


architecture behave of M_generate is
signal c : std_logic_vector(D downto 0);
signal j : integer range 0 to code_period;
signal p : integer range 0 to 15 :=0;
begin
	process(clk)
	begin
		if clk'event and clk='1' then
			if (p<9) then
				p<=p+1;
			--if (load='1') then
				c(D downto 1) <= (others=>'0');
				c(0) <= '1';
				Q <= c(D);
				j<=0;
			elsif j<code_period then 
				j<=j+1;
			else
				--for i in 1 to D loop
				--	c(i) <= c(i-1);
				--end loop;
				c(4) <= c(3);
				c(3) <= c(2);
				c(2) <= c(1);
				c(1) <= c(0);
				c(0) <= c(4) xor c(1);--反饋函數
				Q <= c(D);
				j<=0;
			end if;
		end if;
	end process;
end behave;