?? ask_mod.fit.rpt
字號:
Fitter report for ask_mod
Wed Aug 29 01:15:27 2007
Quartus II Version 6.1 Build 201 11/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Pin-Out File
5. Fitter Resource Usage Summary
6. Input Pins
7. Output Pins
8. I/O Bank Usage
9. All Package Pins
10. Output Pin Default Load For Reported TCO
11. Fitter Resource Utilization by Entity
12. Delay Chain Summary
13. Pad To Core Delay Chain Fanout
14. Control Signals
15. Global & Other Fast Signals
16. Non-Global High Fan-Out Signals
17. Fitter RAM Summary
18. Interconnect Usage Summary
19. LAB Logic Elements
20. LAB-wide Signals
21. LAB Signals Sourced
22. LAB Signals Sourced Out
23. LAB Distinct Inputs
24. Fitter Device Options
25. Fitter Messages
26. Fitter Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------+
; Fitter Summary ;
+------------------------------------+------------------------------------------+
; Fitter Status ; Successful - Wed Aug 29 01:15:26 2007 ;
; Quartus II Version ; 6.1 Build 201 11/27/2006 SJ Full Version ;
; Revision Name ; ask_mod ;
; Top-level Entity Name ; ask_mod ;
; Family ; Cyclone II ;
; Device ; EP2C35F672C7 ;
; Timing Models ; Final ;
; Total logic elements ; 1,789 / 33,216 ( 5 % ) ;
; Total combinational functions ; 1,206 / 33,216 ( 4 % ) ;
; Dedicated logic registers ; 1,756 / 33,216 ( 5 % ) ;
; Total registers ; 1756 ;
; Total pins ; 60 / 475 ( 13 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 213,104 / 483,840 ( 44 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
+------------------------------------+------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings ;
+--------------------------------------------------------+--------------------------------+--------------------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------+--------------------------------+--------------------------------+
; Device ; EP2C35F672C7 ; ;
; Fit Attempts to Skip ; 0 ; 0.0 ;
; Always Enable Input Buffers ; Off ; Off ;
; Router Timing Optimization Level ; Normal ; Normal ;
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