-- Quartus VHDL Template
-- Clearable loadable enablable counter

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY mycounter IS

	PORT
	(
		clk		: IN	STD_LOGIC;
		restart		: IN	STD_LOGIC;
		data		: OUT	STD_LOGIC
	);
	
END mycounter;

ARCHITECTURE a OF mycounter IS

	SIGNAL	count	: INTEGER RANGE 0 TO 1000;
	SIGNAL	temp_data	: STD_LOGIC;

BEGIN

	PROCESS (clk,restart)
	BEGIN
	
		IF restart='1' THEN
		
			count <= 0;
			temp_data<='0';
			
		ELSIF (clk'EVENT AND clk = '1') THEN
			
			if 	count=1000 then
				count<=0;
				temp_data<=not temp_data;
			else			
				count <= count + 1;
			end if;
						
			
		END IF;
		
	END PROCESS;

	data<=temp_data;
END a;