## ================================================================================## Legal Notice: Copyright (C) 1991-2006 Altera Corporation## Any megafunction design, and related net list (encrypted or decrypted),## support information, device programming or simulation file, and any other## associated documentation or information provided by Altera or a partner## under Altera's Megafunction Partnership Program may be used only to## program PLD devices (but not masked PLD devices) from Altera.  Any other## use of such megafunction design, net list, support information, device## programming or simulation file, or any other related documentation or## information is prohibited for any other purpose, including, but not## limited to modification, reverse engineering, de-compiling, or use with## any other silicon devices, unless such use is explicitly licensed under## a separate agreement with Altera or a megafunction partner.  Title to## the intellectual property, including patents, copyrights, trademarks,## trade secrets, or maskworks, embodied in any such megafunction design,## net list, support information, device programming or simulation file, or## any other related documentation or information provided by Altera or a## megafunction partner, remains with Altera, the megafunction partner, or## their respective licensors.  No other licenses, including any licenses## needed under any third party's intellectual property, are provided herein.## ================================================================================#### Generated by: FIR Compiler 6.1## Generated on: 2007-8-29 1:13:39  #START MEGAWIZARD INSERT VARIABLESset megacore_wrapper_dir {F:/program files/altera/61/qdesigns/my_work/ask_mod/}set megacore_lib_dir {f:/program files/altera/61/ip/fir_compiler/lib//ip_toolbench/../}set top_entity fir_ssbset timing_resolution "1ps"set core_version "6.1"set quartus_root_dir {f:/program files/altera/61/quartus//}set device_family "Cyclone II"  set new_flow falseset is_reg_test falseset fir_arch "Distributed Arithmetic : Fully Parallel Filter"#END MEGAWIZARD INSERT VARIABLES## global envif ![info exists env(QUARTUS_ROOTDIR)] {	puts "Expected Enviroment variable QUARTUS_ROOTDIR pointing to a valid Quartus installation"	exit}set q_sim_lib [file join $env(QUARTUS_ROOTDIR) eda sim_lib]# Close existing ModelSim simulation quit -sim# Set simgen model as the default simulation modelif [file exists "auk_megatest_vars.tcl"] {	## I will load the sim_type  "rtl" , "simgen" or "gate_level" through file auk_megatest_vars.tcl## also there will be a variable set family_atom  with the family device  	source auk_megatest_vars.tcl	set development 1	if {![info exists sim_type]} {    puts "wrong contents of auk_megatest_vars.tcl"	} 	set vsim_working_dir $megacore_wrapper_dir	onerror {quit -f}        onbreak {resume}} else {	set development 0	set sim_type "simgen"	## onbreak resume is done to avoid getting the test case stuck during regtesting	onbreak {resume}        onerror {quit -f}	# I have to connect vsim_working_dir	if {[info exists megacore_wrapper_dir]} {		set vsim_working_dir $megacore_wrapper_dir	} else {		puts "Error: megacore_wrapper_dir variable is not defined and not development mode identified: Exiting"		exit	}}if [file exists "auk_do_coverage.tcl"] {	set do_coverage 1} else {	set do_coverage 0}if {![info exists use_ipfs]} {    set use_ipfs 1}cd $vsim_working_dirset quartus_libs [list \                altera_mf {altera_mf_components altera_mf} {altera_mf} 		"$q_sim_lib" 	\		lpm       {220pack 220model}	{220model}	"$q_sim_lib" 	\		sgate	  {sgate_pack sgate} {sgate} 		"$q_sim_lib" 	]		if {[file exists ${top_entity}.vho] && [string match "simgen" $sim_type]} {	puts "Info: IPFS file ${top_entity}.vho found"	set language_ext "vho"	set use_ipfs 1	set flow "simgen"} elseif {[file exists ${top_entity}.vo] && [string match "simgen" $sim_type]} {	puts "Info: IPFS file ${top_entity}.vo found"	set language_ext "vo"	set use_ipfs 1	set flow "simgen"} elseif {[file exists [file join simulation modelsim ${top_entity}.vo]] && [string match "gate_level" $sim_type]} {	puts "Info: Gate Level ${top_entity}.vo found"	set language_ext "vo"	set use_ipfs 0	set flow "gate_level";  # redundant ;-)} elseif {[file exists [file join simulation modelsim ${top_entity}.vho]] && [string match "gate_level" $sim_type]} {	puts "Info: Gate Level ${top_entity}.vho found"	set language_ext "vho"	set use_ipfs 0	set flow "gate_level";  # redundant ;-)} else {	puts "Info: No IPFS nor Gate Level model found. Simulating with RTL pre-compiled development libraries"	set use_ipfs 0	set flow "rtl"}if {$development == 1} {	## I need an environment variable here for the root of the projects	#set base_dir [file join $env(DSP_CORES_LOC) dsp_cores compiled_libs]	set base_dir [file join $env(DSP_CORES_LOC) compiled_libs]	set fir_base_dir [file join $env(DSP_CORES_LOC) FIR src rtl]	set lib_base_dir [file join $env(DSP_CORES_LOC) lib packages]	if {![file exists $base_dir]} {		puts "base_dir not located, Is the environment variable DSP_CORES_LOC defined and properly set?"	}	vmap altera    [file join $base_dir altera]	vmap altera_mf [file join $base_dir altera_mf]	vmap altera_mf_ver [file join $base_dir altera_mf_ver]	vmap lpm [file join $base_dir lpm]	vmap lpm_ver [file join $base_dir lpm_ver]	if {[string match $flow "gate_level"]} {		vmap $family_atom [file join $base_dir $family_atom]	}}if {($use_ipfs == 1) && ([vsimAuth] != "ALTERA")} {	foreach {lib file_vhdl_list file_verilog_list src_files_loc} $quartus_libs {		vlib $lib		vmap $lib $lib		if {[string match "vho" $language_ext]} {			foreach file_item $file_vhdl_list {				# in here I should use a device family parameter to just compile the required library only (optional)				catch {vcom -explicit -93 -work $lib [file join $src_files_loc ${file_item}.vhd]} err_msg				if {![string match "" $err_msg]} {return $err_msg}			}		} elseif {[string match "vo" $language_ext]} {			foreach file_item $file_verilog_list {				catch {vlog -work $lib [file join $src_files_loc ${file_item}.v]} err_msg				if {![string match "" $err_msg]} {return $err_msg}			}		}	}}catch {	vdel -lib fir_work -all}if {$development == 1} {	#vlog -work altera_mf_ver -refresh	vmap auk_dspip_lib [file join $base_dir auk_dspip_lib]	#vcom -work auk_dspip_lib -refresh	vmap fir_verilog_lib [file join $base_dir fir_verilog_lib]	#vlog -work fir_verilog_lib -refresh}if {[file exist fir_work] ==0} 	{  exec vlib fir_work  exec vmap fir_work fir_work}# gather generated filesif {($development == 1) && ![string match $flow "gate_level"]} {	# this files go to library  auk_dspip_fir_lib		set auk_dspip_fir_lib_files {		fu/adder/rtl auk_dspip_accumulator.vhd 		fu/adder/rtl auk_dspip_adder_tree.vhd 		fu/adder/rtl auk_dspip_adders.vhd 		fu/avalon/rtl auk_dspip_avalon_slave_write.vhd 		fu/dsp_block/rtl auk_dspip_dspblock_bank.vhd 		fu/memory/rtl auk_dspip_coef_banks_fixed.vhd 		fu/memory/rtl auk_dspip_data_memory_bank.vhd 		fu/memory/rtl auk_dspip_memory_single.vhd 		fu/memory/rtl auk_dspip_memory_true_dual.vhd 	./ auk_dspip_fir_top_dec_half_sym.vhd }		if {[string match "true" $new_flow]} {		if {[file exist auk_dspip_fir_lib] ==0} 	{			exec vlib auk_dspip_fir_lib			exec vmap auk_dspip_fir_lib auk_dspip_fir_lib		}		## Compile package_definitions_fir into fir_work and have work mapped into fir_work.		exec vmap work fir_work		exec vmap auk_dspip_fir_lib fir_work		vcom -93  -work auk_dspip_fir_lib [file join $fir_base_dir packages auk_dspip_fir_math_pkg.vhd]		vcom -93  -work auk_dspip_fir_lib [file join $megacore_wrapper_dir fir_definitions_pkg.vhd]		vcom -93  -work auk_dspip_fir_lib [file join $fir_base_dir packages auk_dspip_fir_lib_pkg.vhd]				foreach {loc i} $auk_dspip_fir_lib_files {			vcom -93  -work auk_dspip_fir_lib [file join $fir_base_dir $loc $i]		}	}			## here now for 6.1 there are vhd files as well as verilog files!!	set gen_files_verilog [glob "${top_entity}*.v"]	foreach i $gen_files_verilog {		vlog  -work fir_work $i	}	## are there VHDL files?	set gen_files_vhdl [glob "${top_entity}*.vhd"]	foreach i $gen_files_vhdl {		vcom  -93 -work fir_work $i	}	# this should be done by now	#vcom -93  -work fir_work [file join $megacore_wrapper_dir ${top_entity}_new.vhd]	if {[file exist "${top_entity}.vhd"]} {		set hdl_extension ".vhd"		vcom  -93 -work fir_work ${top_entity}.vhd	} elseif {[file exist "${top_entity}.v"]} {		set hdl_extension ".v"		vlog  -work fir_work ${top_entity}.v	}	} else {	# IPFS flow here		if {[string match $flow "simgen"]} {    if {[string match $language_ext "vho"]} {vcom -93 -work fir_work [file join $megacore_wrapper_dir ${top_entity}.vho] }    if {[string match $language_ext "vo"]}  {vlog -work fir_work [file join $megacore_wrapper_dir ${top_entity}.vo] }	} elseif {[string match $flow "gate_level"]} {		if {[string match $language_ext "vho"]} {			vcom -93 -work fir_work [file join $megacore_wrapper_dir simulation modelsim ${top_entity}.vho]		}		if {[string match $language_ext "vo"]} {			vlog -work fir_work [file join $megacore_wrapper_dir simulation modelsim ${top_entity}.vo]		}	}}## now compiling VHDL atlantic components and new top level# find out wrapper language#vcom -93 top_learn.vho# Testbench only in verilog at the moment #vlog -work fir_work tb_${top_entity}.v# testbench developed in VHDL for Avalon Streaming , compiling componentsif {[file exist "${top_entity}.vhd"]} {    if {[string match $is_reg_test "true"]} {			set tb_components {			auk_dspip_avalon_streaming_source_model.vhd			auk_dspip_avalon_streaming_sink_model.vhd			}       set model_dir [file join $env(DSP_CORES_LOC) lib models avalon_streaming]		foreach i $tb_components {			vcom -93  -work fir_work [file join $model_dir $i]		}   }	} # Actual top level testbench vcom -93  -work fir_work [file join $megacore_wrapper_dir tb_${top_entity}.vhd]#vcom -93  -work fir_work [file join "d:/data/projects/FIR/testbenches" tb_top_avalon_st.vhd] set vsim_cmd vsim#if {[string match -nocase ".v" $hdl_extension] && ([vsimAuth] != "ALTERA") && [string match $flow "simgen"]} {#	lappend vsim_cmd "-L" "Sgate" "-L" "altera_mf" "-L" "lpm"#}	elseif {[string match -nocase ".v" $hdl_extension] && ([vsimAuth] == "ALTERA") && [string match $flow "simgen"]} {#	lappend vsim_cmd "-L" "Sgate_ver" "-L" "altera_mf_ver" "-L" "lpm_ver"#}if {[string match $flow "simgen"]} {	lappend vsim_cmd "-L" "Sgate" "-L" "altera_mf" "-L" "lpm" "-L" "auk_dspip_lib" "-L" "fir_work"} if {[string match $flow "rtl"] && [string match $new_flow "false"]} {	lappend vsim_cmd "-L" "fir_verilog_lib" "-L" "altera_mf_ver" "-L" "lpm_ver"}if {[string match $flow "rtl"] && [string match $new_flow "true"]} {	lappend vsim_cmd "-L" "altera_mf" "-L" "lpm" "-L" "auk_dspip_lib" "-L" "auk_dspip_fir_lib" }if {[string match $flow "gate_level"]} {	lappend vsim_cmd "-L" "Sgate" "-L" "altera_mf" "-L" "lpm" "-L" "auk_dspip_lib" "-L" "$family_atom" "-L" "fir_work"	if {[file exists [file join . simulation modelsim ${top_entity}_vhd.sdo]]} {		lappend vsim_cmd "-sdftyp" "/tb_${top_entity}/DUT=./simulation/modelsim/${top_entity}_vhd.sdo"	}} #lappend vsim_cmd "FIR_work.tb_${top_entity}" "-t" "$timing_resolution"lappend vsim_cmd "FIR_work.tb_${top_entity}" "-t" "$timing_resolution"catch {	eval $vsim_cmd } vsim_msgputs $vsim_msg# waveform formation##  I would like to load this waveforms only in interactive mode## in testing mode they shouldn't be loaded.   TBDif {[file exists "wave.do"]} {do wave.do} else {add wave sim:/tb_${top_entity}/*if {[string match $is_reg_test "true"]} {add wave -noupdate -divider {tb_sink}add wave sim:/tb_${top_entity}/sink_model/*add wave -noupdate -divider {tb_source}add wave sim:/tb_${top_entity}/source_model/* }if {[string match $flow "rtl"]} {add wave -noupdate -divider {top_wrapper}add wave sim:/tb_${top_entity}/dut/${top_entity}_new_inst/*add wave -noupdate -divider {top_wrapper_sink}add wave sim:/tb_${top_entity}/dut/${top_entity}_new_inst/sink/*add wave -noupdate -divider {top_wrapper_source}add wave sim:/tb_${top_entity}/dut/${top_entity}_new_inst/source/*add wave -noupdate -divider {top_wrapper_intf_ctrl}add wave sim:/tb_${top_entity}/dut/${top_entity}_new_inst/intf_ctrl/*add wave -noupdate -divider {${top_entity}_core}add wave sim:/tb_${top_entity}/dut/${top_entity}_new_inst/fir_core/*}}## end waveform formationset StdArithNoWarnings 1run 0 nsset StdArithNoWarnings 0catch {run -all} run_msgputs $run_msg#vsim  -L tb_top_learn -t 1ps # this file doesn't exists#do top_learn_wave.do# I have to make it run -all and have the test bench take care of the finish #run 108700nsif [file exists "auk_finish_msim_run.tcl"] {source auk_finish_msim_run.tcl}