?? ask_mod.flow.rpt
字號:
Flow report for ask_mod
Wed Aug 29 01:16:13 2007
Quartus II Version 6.1 Build 201 11/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow Log
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+------------------------------------------+
; Flow Status ; Successful - Wed Aug 29 01:16:13 2007 ;
; Quartus II Version ; 6.1 Build 201 11/27/2006 SJ Full Version ;
; Revision Name ; ask_mod ;
; Top-level Entity Name ; ask_mod ;
; Family ; Cyclone II ;
; Device ; EP2C35F672C7 ;
; Timing Models ; Final ;
; Met timing requirements ; Yes ;
; Total logic elements ; 1,789 / 33,216 ( 5 % ) ;
; Total combinational functions ; 1,206 / 33,216 ( 4 % ) ;
; Dedicated logic registers ; 1,756 / 33,216 ( 5 % ) ;
; Total registers ; 1756 ;
; Total pins ; 60 / 475 ( 13 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 213,104 / 483,840 ( 44 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
+------------------------------------+------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 08/29/2007 01:13:53 ;
; Main task ; Compilation ;
; Revision Name ; ask_mod ;
+-------------------+---------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+----------------------------------------+---------------------------------------------------------------------------------------+---------------+-----------------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+----------------------------------------+---------------------------------------------------------------------------------------+---------------+-----------------------+------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; Off ; On ; lc_tdl_en ; -- ;
; AUTO_SHIFT_REGISTER_RECOGNITION ; Off ; On ; lc_tdl_mr ; -- ;
; AUTO_SHIFT_REGISTER_RECOGNITION ; Off ; On ; lc_tdl_strat ; -- ;
; AUTO_SHIFT_REGISTER_RECOGNITION ; Off ; On ; lc_tdl_strat_cen ; -- ;
; AUTO_SHIFT_REGISTER_RECOGNITION ; Off ; On ; mlu_nd_lc ; -- ;
; AUTO_SHIFT_REGISTER_RECOGNITION ; On ; On ; msft_data ; -- ;
; AUTO_SHIFT_REGISTER_RECOGNITION ; Off ; On ; sadd ; -- ;
; AUTO_SHIFT_REGISTER_RECOGNITION ; Off ; On ; sadd_cen ; -- ;
; AUTO_SHIFT_REGISTER_RECOGNITION ; Off ; On ; sadd_lpm ; -- ;
; AUTO_SHIFT_REGISTER_RECOGNITION ; Off ; On ; sadd_lpm_cen ; -- ;
; AUTO_SHIFT_REGISTER_RECOGNITION ; Off ; On ; sadd_lpm_reg_top_cen ; -- ;
; AUTO_SHIFT_REGISTER_RECOGNITION ; Off ; On ; sadd_reg_top ; -- ;
; AUTO_SHIFT_REGISTER_RECOGNITION ; Off ; On ; sadd_reg_top_cen ; -- ;
; AUTO_SHIFT_REGISTER_RECOGNITION ; Off ; On ; tdl_da_lc ; -- ;
; AUTO_SHIFT_REGISTER_RECOGNITION ; Off ; On ; tsadd ; -- ;
; AUTO_SHIFT_REGISTER_RECOGNITION ; Off ; On ; tsadd_lpm ; -- ;
; AUTO_SHIFT_REGISTER_RECOGNITION ; Off ; On ; tsadd_lpm_cen ; -- ;
; AUTO_SHIFT_REGISTER_RECOGNITION ; Off ; On ; tsadd_lpm_reg_top_cen ; -- ;
; AUTO_SHIFT_REGISTER_RECOGNITION ; Off ; On ; tsadd_reg_top ; -- ;
; AUTO_SHIFT_REGISTER_RECOGNITION ; Off ; On ; tsadd_reg_top_cen ; -- ;
; DSP_BLOCK_BALANCING ; Logic Elements ; Auto ; fir_ssb_st ; -- ;
; EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL ; IBIS (Signal Integrity) ; <None> ; -- ; -- ;
; USER_LIBRARIES ; F:/program files/altera/61/ip/fir_compiler/lib;F:/program files/altera/61/ip/nco/lib; ; -- ; -- ; -- ;
+----------------------------------------+---------------------------------------------------------------------------------------+---------------+-----------------------+------------+
+----------------------------------------+
; Flow Elapsed Time ;
+-------------------------+--------------+
; Module Name ; Elapsed Time ;
+-------------------------+--------------+
; Analysis & Synthesis ; 00:00:51 ;
; Fitter ; 00:00:39 ;
; Assembler ; 00:00:21 ;
; Classic Timing Analyzer ; 00:00:02 ;
; EDA Netlist Writer ; 00:00:15 ;
; Total ; 00:02:08 ;
+-------------------------+--------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off ask_mod -c ask_mod
quartus_fit --read_settings_files=off --write_settings_files=off ask_mod -c ask_mod
quartus_asm --read_settings_files=off --write_settings_files=off ask_mod -c ask_mod
quartus_tan --read_settings_files=off --write_settings_files=off ask_mod -c ask_mod --timing_analysis_only
quartus_eda --read_settings_files=off --write_settings_files=off ask_mod -c ask_mod
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