# Copyright (C) 1991-2004 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.


# The default values for assignments are stored in the file
#		ask_mod_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:04:44  DECEMBER 25, 2005"
set_global_assignment -name LAST_QUARTUS_VERSION 6.1

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name TOP_LEVEL_ENTITY ask_mod

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP2C35F672C7

# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"

# Simulator Assignments
# =====================

# LogicLock Region Assignments
# ============================
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF

# -----------------------------------------
# start EDA_TOOL_SETTINGS(eda_board_design)

	# EDA Netlist Writer Assignments
	# ==============================

# end EDA_TOOL_SETTINGS(eda_board_design)
# ---------------------------------------

set_global_assignment -name USER_LIBRARIES "F:/program files/altera/61/ip/fir_compiler/lib;F:/program files/altera/61/ip/nco/lib;"
set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "IBIS (Signal Integrity)"
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION ON -entity msft_data
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tdl_da_lc
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity sadd_lpm
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd_lpm
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity sadd_lpm_cen
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd_lpm_cen
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity sadd
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity lc_tdl_strat
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity lc_tdl_mr
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity lc_tdl_en
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity lc_tdl_strat_cen
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity sadd_reg_top_cen
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd_reg_top_cen
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity sadd_cen
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity sadd_reg_top
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd_reg_top
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd_lpm_reg_top_cen
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity sadd_lpm_reg_top_cen
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity mlu_nd_lc
set_global_assignment -name DSP_BLOCK_BALANCING "LOGIC ELEMENTS" -entity fir_ssb_st
set_global_assignment -name VHDL_FILE pie_code.vhd
set_global_assignment -name BDF_FILE ask_mod.bdf
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE pie_code_test.vwf
set_global_assignment -name VHDL_FILE "F:/program files/altera/61/qdesigns/my_work/ask_mod/auk_dspip_lib_pkg.vhd"
set_global_assignment -name VHDL_FILE "F:/program files/altera/61/qdesigns/my_work/ask_mod/auk_dspip_math_pkg.vhd"
set_global_assignment -name VHDL_FILE "F:/program files/altera/61/qdesigns/my_work/ask_mod/auk_dspip_avalon_streaming_sink.vhd"
set_global_assignment -name VHDL_FILE "F:/program files/altera/61/qdesigns/my_work/ask_mod/auk_dspip_avalon_streaming_source.vhd"
set_global_assignment -name VHDL_FILE "F:/program files/altera/61/qdesigns/my_work/ask_mod/auk_dspip_avalon_streaming_controller.vhd"
set_global_assignment -name VERILOG_FILE "F:/program files/altera/61/qdesigns/my_work/ask_mod/fir_ssb_st.v"
set_global_assignment -name VHDL_FILE "F:/program files/altera/61/qdesigns/my_work/ask_mod/fir_ssb_new.vhd"
set_global_assignment -name VERILOG_FILE "F:/program files/altera/61/qdesigns/my_work/ask_mod/fir_ssb.v"
set_global_assignment -name VECTOR_TABLE_OUTPUT_FILE final2_sim_ssbnnnn.tbl
set_global_assignment -name VERILOG_FILE "F:/program files/altera/61/qdesigns/my_work/ask_mod/nco1_st.v"
set_global_assignment -name VHDL_FILE "F:/program files/altera/61/qdesigns/my_work/ask_mod/nco1.vhd"
set_global_assignment -name SETUP_HOLD_DETECTION OFF