library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity sample is

port(clk : in std_logic;
--	load : in std_logic;--實際板子沒復位信號
	I : in std_logic_vector(13 downto 0);
	Q : out std_logic_vector(13 downto 0));
end sample;


architecture behave of sample is
begin
	process(clk)
	begin
		if clk'event and clk='1' then
			Q(13 downto 0)<=I(13 downto 0);
		end if;
	end process;
end behave;